Abstract: An amplifier circuit arrangement comprises first and second long-tailed pairs of transistors each including an inductor to provide a constant current source for their respective transistor pair. Each of the transistors of the pairs is provided with a bias current on its base electrode. A differential input signal is applied between the base electrode of one transistor, via a dc blocking capacitor and an input terminal, and the base electrode of another transistor, via a dc blocking capacitor and an another input terminal. The collector electrodes of two of the transistors are connected together and to an output terminal. The collector electrodes of the other two transistors similarly are connected together and to the other output terminal. A differential output signal is provided between the output terminals. This connection of the collectors of the transistors, which can be described as parallel connection, provides summation of the differential signals provided by the transistor pairs.

Abstract: An image reject mixer arrangement 1 comprises a transconductor 2, first and second mixer cores 3 and 4, first and second phase shifters 5 and 6 and a summer or combiner 7. The mixer arrangement 1 receives a single-ended RF voltage signal on a terminal 8, a differential local oscillator signal on I-LO terminals indicated at 9 and a 90° phase shifted differential local oscillator signal on Q-LO terminals 10, and provides differential IF output signals on output terminals 11. From the output of the transconductor 2 to the output of the combiner 7, the image reject mixer arrangement 1 carries signals in what can be described as a “current mode”, i.e. it is the current, not the voltage, which conveys the desired signal. In this current mode, it is advantageous to provide each active circuit block with a high output impedance and a low input impedance wherever possible.

Abstract: An oscillator comprising an oscillator body having a waveguide and a substantially cylindrical bore intersecting the waveguide, and a package comprising a heat sink having a substantially cylindrical portion and an oscillatory semiconductor device supported at one end of the heat sink. The diameter of the cylindrical portion of the heat sink in relation to the diameter of the bore is such that the heat sink is supported in the bore by one of an interference fit and a tight sliding fit, with the semiconductor device being located in the waveguide. The tight sliding fit or interference fit includes a layer of soft deformable material.

Abstract: A method of manufacturing integrated circuits is performed by coating a substrate with resist, exposing the resist to light through a pattern in a mask so as to define slots in the resist corresponding to the pattern in the mask, chemically developing the resist after exposure to light, and choosing the thickness of the resist so as to achieve the desired profile of the slots defined in the resist.

Abstract: In a multi-channel electrical communication system 1, a method of estimating the interference level in a test channel due to the intermodulation of two or more other channels, where each channel is centred upon a carrier frequency. The method comprises, for a given m-th order mode, an initial step of identifying the set(s) of carrier frequencies, the m-th order linear combination of which gives rise substantially to the carrier frequency of said test channel. This process is carried out by a computer 2. For the or each of the identified set of carrier frequencies, signal generators 3 are tuned to respective ones of the carrier frequencies. The generated signals are applied to an input of the communication system 1, and the intermodulation interference at the carrier frequency of the test channel is measured at an output of the system 1.

Abstract: An AC voltage amplifier arrangement comprising an input stage 1 having an input, an amplifier 3 connected in series shunt feedback mode, and an output, further comprises a variable gain amplification stage 2 having an input coupled to the output of said input stage 1, and an output. The amplifiers 3, 5 of the input and variable gain amplification stages 1, 2 are arranged to operate in current mode.

Abstract: An integrated circuit comprises an application-non-specific library cell, externally developed logic circuitry integrated with the library cell, and an up-integration module (UIM) connected to the library cell and to the logic circuitry and providing a two-way interface between the library cell and the logic circuitry and between the library cell and an external device. The logic developed for a prototype system comprising such a library cell in association with external logic circuitry can be integrated into the circuit without requiring any change in its function or in the program code developed for the prototype system.

Abstract: A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidising the silicon surface, and subsequently removing the oxide to leave the recess.

Abstract: A radio frequency amplifier comprises an input amplifier provided with a shunt feedback path for determining the input impedance. A first transconductance amplifier forms part of a series feedback arrangement with a resistor around the amplifier so as to boost the effective value of the resistor. An identical transconductance amplifier is connected to the output of the input amplifier and its output forms the output of the radio frequency amplifier.

Abstract: In a detection circuit for ASK or OOK modulation, the received modulated signal is ac coupled to a dc restoration circuit and amplified. The dc restoration is carried out on signal peaks corresponding to “mark” intervals of the modulated signal. Thus data may be recovered even in the presence of high levels inband continuous interfering signals.

Abstract: A 4-level direct conversion receiver demodulator 1 comprises an edge detector 2, a finite impulse response filter 3, an N-bit path 4, a data slicer 5 and automatic frequency control device 6. The edge detector 2 receives Limited I (LIMI) and Limited Q (LIMQ) signals on respective ones of first and second input leads 7 and 8 from a direct conversion receiver arrangement R. The edge detector 2 contains logic to provide an EDGE signal, comprising a short pulse when any edge is detected in either of the LIMI and LIMQ signals, on a line 9 and an I Lead Q (ILQ) signal, indicative of which of the LIMI and LIMQ signals has the leading phase, on a line 10 to the filter 3. The edge detector 2 thus determines both the frequency and the relative phase of the signals provided by the limited output direct conversion receiver R without the use of analogue to digital conversion circuitry. The N-bit path output 4 from the filter 3 is provided to both the data slicer 5 and to the AFC device 6.

Abstract: An image reject mixer for a radio receiver comprises transconductors 21 and 22, mixer stages 30 and 23 and a phase shift and combiner circuit 26. The transconductors 21 and 22 provide differential output current signals to their respective mixer stage 30 and 23. Capacitors 28 and 29 are connected between equivalent outputs of the transconductors 21 and 22 respectively. The capacitors 28 and 29 have the effect of correlating the output noise of the transconductors 21 and 22 and correlating the noise generated by the mixer stage transistors which is leaked to the inputs of the mixer stages 30 and 23, the image frequency components of which noise are thereby cancelled by the operation of the mixer stages 30 and 23 and the phase shift and combiner circuit 26. The capacitors 28 and 29 also compensate the second harmonic of the local oscillators which leak through to the inputs of the mixer stages 30 and 23. Overall, gain, noise figure and linearity can all be improved without an increase in current consumption.

Abstract: Circuit 200 comprises an input amplifier stage 290, phase-splitters 292, 293 and mixer cores 294, 295. An input signal is applied to terminal 220, a local oscillator signal applied to terminals 230, 231 and a 90° shifted local oscillator signal is applied to terminals 232, 233. The In-phase differential signal is output at terminals 240, 241 and the quadrature signal is output at terminals 240, 233. Phase-splitters 292, 293 comprise base-coupled transistors 202, 203, 205, 206 which are biased by a potential applied to terminal 262. As these phase-splitters are driven by input amplifier stage 290, which acts as a current source, the arrangement has very good noise properties. Degeneration inductor 280 reduces the noise figure of the circuit further because it is a noiseless component.

Abstract: A variable transconductance amplifier comprises transistors and whose emitters are connected via resistors and to a constant current source to form a differential or long tail pair. A feedback amplifier whose transconductance is controllable has inputs connected to the collectors of the transistors and outputs connected to the emitters thereof. The feedback amplifier thus supplies a differential current to the emitters of the transistors which corresponds to the product of the differential output signal of the transistors and the variable transconductance of the feedback amplifier.

Abstract: A voltage to current converter comprises a first long tail pair comprising transistors whose emitters are connected via equal value resistors to a constant current source. The first long tail pair forms a main transconductance stage. A subsidiary or corrector transconductance stage is connected in anti-phase with the main stage. The corrector stage is based on another long tail pair comprising transistors whose emitters are connected via resistors to another constant current source. The linear part of the transconductance of the corrector stage is substantially less than that of the main stage but the non-linear part is substantially equal to that of the main stage. Thus, non-linear distortion can be substantially reduced.

Abstract: A MOS-controllable power semiconductor trench device has a gate in the form of a trench which extends through a region of p type silicon into an n type region of low conductivity. A discontinous buried p layer below the bottom of the trench forms part of a thyristor which in operation is triggered into conduction by conduction of a PIN diode which is produced when an accumulation layer is formed in the n type region adjacent to the trench under the action of an on-state gate signal. The device has a high on-state conductivity and is protected against high voltage breakdown in its off-state by the presence of the buried layer. An off-state gate signal causes removal of the accumulation layer and conduction of the PIN diode and the thyristor ceases in safe, reliable and rapid manner.

Abstract: A synchronous single port random access memory comprises a core 2 of memory cells 3 arranged as rows and columns. The rows are addressed by a row decoder 5 and the memory cell outputs are connected as columns to a column decoder and multiplexer 7. The decoder and multiplexer 7 selects groups of memory cells 3 from the addressed row and connects these to sense amplifiers 8. Changes in address are propagated immediately to the core 2 so that the selected memory cells 3 are connected as quickly as possible and without any fixed delays to the sense amplifiers 8. Similarly, a read clock “rclk” enables the sense amplifiers 8 immediately upon becoming active.

Abstract: A number of npn and pnp bipolar transistors is formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others. The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidizing the silicon surface, and subsequently removing the oxide to leave the recess.

Abstract: A semiconductor memory, for example of the ROM type, has columns of memory cells with a bitline for each column connected to the cells of the column. The bitlines are connected via multiplexers to the input of a sense amplifier. Before column selection, the bitlines are held uncharged. When a column is selected, its bitline is connected to a charging voltage by a pull up transistor.

Abstract: A variable attenuator comprises bipolar transistors Q1 and Q2 connected in reverse parallel between a point 1 and ground potential G. The base electrodes of the transistors Q1 and Q2 are biased independently by a control circuit 3. The collector of transistor Q1 and the emitter of transistor Q2 are commonly connected to a bias voltage provided by resistor R2 and voltage source Vr. The attenuator provides means by which the linearity, gain, power handling capabilities and noise figure of a front-end receiver can be altered. The attenuator is susceptible to integration in, for example, a radio receiver front-end.