Patents Assigned to Mitsubhisi Denki Kabushiki Kaisha
  • Patent number: 5548153
    Abstract: Upward and downward variation of a threshold voltage of a TFT is effectively suppressed by a semiconductor device and a method of manufacturing the same. In the semiconductor device, a conductive layer is formed on the substantially same plane as a semiconductor layer forming a channel region and source/drain regions of the TFT, and is spaced from the semiconductor layer by a predetermined distance. A predetermined potential is applied to the conductive layer. Thereby, an electric field is applied from the conductive layer to the channel region of the TFT, so that variation of the threshold voltage of the TFT is effectively prevented.
    Type: Grant
    Filed: November 27, 1995
    Date of Patent: August 20, 1996
    Assignee: Mitsubhisi Denki Kabushiki Kaisha
    Inventor: Takeo Muragishi