Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: A pixel interpolation circuit according to this invention includes a plurality of interpolation circuits each calculating interpolation candidate data of a interpolation pixel and test interpolation data of a plurality of pixels neighboring the interpolation pixel using different interpolation methods, a determining circuit for selecting one of the interpolation circuits based on a difference between the test interpolation data and actual pixel data, and an output circuit for outputting the interpolation candidate data calculated by the selected interpolation circuit as the interpolation pixel data.

Abstract: A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.

Abstract: A device for detecting whether addresses used for accessing in a memory mapped I/O system are present in the I/O area or not is provided. The device includes a mask register for logically ANDing with an incoming address. The output of the ANDing process is exclusive-ORed with an I/O address register. When an operand fetch is made to an I/O area the fetch is suspended during execution of preceding instructions. When the instruction fetch unit seeks an I/O area address, or the address calculation unit seeks an I/O area address, or data is fetched across a boundary of the I/O area, an exception is activated.

Abstract: Two or three trenches are formed in a silicon substrate, and a conductive layer is formed in the silicon substrate facing the trenches. An oxide film for insulation is formed on a surface of the conductive layer facing the trenches. The trenches are filled with polysilicon, and the conductive layer and the polysilicon constitute a capacitor through the oxide film. Since this capacitor has two or three trenches, an effective area sufficiently large for increasing a capacitance value of the capacitor can be obtained without increasing the plane area of the device. The conductive layer and the polysilicon are connected to aluminum interconnection layers through a silicide layer, so as to be connected to other integrated circuits.