Patents Assigned to Mitsubishi Denki Kabuchiki Kaisha
  • Patent number: 4152711
    Abstract: A p type semiconductor gate layer is buried in an N type semiconductor cathode layer to encircle a channel through which the forward current of a luminescent PN junction passes. A reverse voltage is applied to the gate layer to spread a depletion layer in the channel to control the forward current and therefore the emission of light. The gate layer may be disposed on that surface of the cathode layer remote from the luminescent PN junction with a groove disposed the other surface of the cathode layer to narrow the channel.
    Type: Grant
    Filed: March 25, 1977
    Date of Patent: May 1, 1979
    Assignee: Mitsubishi Denki Kabuchiki Kaisha
    Inventor: Josuke Nakata