Patents Assigned to Mitsubishi Denki Kabushik Kaisha
  • Publication number: 20060254294
    Abstract: An air conditioning apparatus has plural indoor units having: plural heat exchangers; and flow controllers respectively corresponding to the heat exchangers. In each of the indoor units, one heat exchanger is used as a condenser, and another heat exchanger is used as an evaporator, thereby causing the indoor unit to perform a temperature and humidity controlling operation. An indoor unit(s) which is not set to perform the temperature and humidity controlling operation may be caused to perform a heating operation or a cooling operation. Capacity controls on the condensers and the evaporators are performed by corresponding flow controllers. Gas refrigerants ejected from plural heat exchangers serving as evaporators are joined together, and then distributed to plural heat exchangers serving as condensers.
    Type: Application
    Filed: October 30, 2002
    Publication date: November 16, 2006
    Applicant: MITSUBISHI DENKI KABUSHIK KAISHA
    Inventors: Daisuke Shimamoto, Munehiro Yamanaka, Hidekazu Tani, Tomohiko Kasai, Masahiro Tsuda, Shuji Oura, Makoto Saitou
  • Patent number: 6347620
    Abstract: In an EGR valve or an ISC valve used as a control valve assembly for regulating the flow amount of a controlled fluid flowing through an internal combustion engine of an automobile, etc.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: February 19, 2002
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventor: Toshihiko Miyake
  • Patent number: 5522056
    Abstract: A cache memory with a data memory divided into a plurality of word arrays, each of which is selectable by a word select indicator. Each word array is further divided into a plurality of bit arrays, each of which correspond to a bit of a word, and include congruence set memories for each congruence set. A bit array is connected to a sense amplifier via a congruence set selector, thereby one set of congruence set memories of the word arrays in the data memory is selected, and one congruence set memory is selected from each of the bit arrays by a congruence set selector to be connected with a sense amplifier, so that only one sense amplifier has to be provided for each bit in each word in an entry of the data memory, thus eliminating the need to increase the number sense amplifiers as the number of congruence sets increases. Furthermore, as only the sense amplifier associated with the selected word array is operational, current consumption is reduced.
    Type: Grant
    Filed: August 3, 1993
    Date of Patent: May 28, 1996
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventors: Tetsuya Watanabe, Akira Yamada
  • Patent number: 5470764
    Abstract: To manufacture a semiconductor device a first insulating oxide film and a second thicker insulating oxide film, which continues to the first insulating oxide film, are formed on a semiconductor substrate. The first and second insulating oxide films are covered by a polysilicon film selectively formed on a patterned nitride layer or formed over the semiconductor substrate. In the second case, a silicon nitride film is formed in the lowermost layer portion of the polysilicon film by implanting nitrogen ions and then applying a heat treatment. The polysilicon and silicon nitride films are patterned for forming first and second polysilicon resistance films on the first and second insulating oxide films, respectively. A first electrode is connected to the first polysilicon resistance film and a second electrode is connected to the second polysilicon resistance film.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: November 28, 1995
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventors: Masaaki Ikegami, Tetsuo Higuchi
  • Patent number: 5289070
    Abstract: The brush holder 12 of a brush device for a d.c. machine is provided with plural pairs of brush boxes 12a each having an open front portion and an open inner diameter portion, and a pair of projections 12d at outer portions; lead wires 14a, 14b for each pair of brushes 13a and 13b have such length that they can avoid interference with the projections 12d, and the brushes 13a, 13b can be fitted to the brush boxes 12 from the front side and in the axial direction of the brush holder 12; brush springs 15 are put at the top portion of the brushes 13a, 13b; and an insulating plate 16 is attached to the front of the brush holder 12, whereby assembling work for the brushes 13a, 13b can be automated.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: February 22, 1994
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventors: Shigeru Shiroyama, Akira Kuragaki
  • Patent number: 5281847
    Abstract: A semiconductor structure comprises a gate-turn-off thyristor region (GR) and a diode region (DR) with an isolation area (SR) therebetween. The isolation area is provided with a multistage groove (30) having step structures (34,35). The multistage groove is formed through a two-stage etching process, and over-etched regions in the bottom corners of the multistage groove are relatively shallow ones. This structure is effective for increasing the breakdown voltage of the semiconductor structure and isolations between a the gate-turnoff thyristor region and the diode region.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: January 25, 1994
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventor: Futoshi Tokunoh
  • Patent number: 5063305
    Abstract: In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuits), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.
    Type: Grant
    Filed: April 14, 1989
    Date of Patent: November 5, 1991
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventors: Hiroshi Minami, Koreaki Fujita
  • Patent number: 4612493
    Abstract: A control device for an alternator which can be fabricated as a single hybrid integrated circuit. The output of the alternator which is to be used to drive the field coil of the generator is rectified, and the rectified voltage is voltage divided by two resistors, one of which has a smoothing capacitor connected in parallel therewith. A detection and amplification transistor amplifies the signal at the junction point of the resistors and applies the amplified signal through a Zener diode to the base of a control transistor, the latter driving a switching transistor which controls the amount of current passing through the field coil of the generator.
    Type: Grant
    Filed: May 8, 1984
    Date of Patent: September 16, 1986
    Assignee: Mitsubishi Denki Kabushik Kaisha
    Inventors: Tadashi Katashima, Yoshiyuki Iwaki