Abstract: When an operation test is performed to a plurality of circuit blocks each having the same circuit configuration, common test pattern data is transmitted to the respective circuit blocks through corresponding selector circuits.

Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Abstract: A semiconductor module is provided with a module substrate, a plurality of semiconductor chips formed on the module substrate, and a mold resin formed so as to integrally cover the plurality of semiconductor chips. Then, a plurality of trenches is formed on the main surface of the module substrate, so as to be parallel to one side forming the main surface, on the side on which the bare chips are formed. Thereby, a semiconductor module can be obtained wherein it is possible to restrict separation of the mold resin from the module substrate.

Abstract: A shallow P well and a deep P well are formed in the surface of a P type semiconductor substrate so as to partially overlap each other and these wells are surrounded by an N well, a deep bottom N type well and a connection N well. The impurity concentration of this overlapping region is higher than the impurity concentration of the P well or of the deep P well and a P+ type region is formed in the surface of the overlapping region. A potential (VBB) different from the ground potential is applied to the P+ type region. The P+ type region is formed in overlapping region and, thereby, the layout of the semiconductor device can be scaled down.

Abstract: A semiconductor device includes a constant voltage generation circuit generating a constant voltage commonly to reference voltages corresponding to a plurality of internal voltages. The plurality of reference voltages are generated from the common constant voltage. Thus, the semiconductor device for generating internal voltages is implemented, which allows reduction in layout area and decrease in test time for voltage adjustment.

Abstract: With power-on detection circuits provided for a plurality of power supply voltages, a main power-on detection signal is maintained at the active state to reset an internal node while at least one of the power-on detection signals is active. In a multi-power semiconductor integrated circuit device, current consumption at the time of power-up is reduced.

Abstract: A plurality of pump modules are provided, the number of pump modules to be activated is changed depending on a mode of operation, and the number of pump modules to be activated is also adjusted with the specification of interest taken into consideration. There can be provided an internal voltage generation circuit occupying a small area and readily capable of accommodating a change in specification.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: In a three-state circuit issuing a shared gate signal, after an N-channel MOS transistor charges a node issuing an output signal OUT to external power supply potential exvdd, the N-channel MOS transistor is turned off, and a P-channel MOS transistor is turned on to charge the node to boosted potential VPP. Thereby, a power consumed at boosted potential VPP can be reduced, and sizes of transistors of a VPP generating circuit can be reduced. Thereby, a semiconductor memory device having a small chip size can be achieved.