Patents Assigned to Mitsubishi Denki Kabushiki Kaisha and
  • Publication number: 20030189964
    Abstract: One of the embodiments of the present invention has a purpose to provide a kink-free semiconductor optical device stabilizing a laser oscillation and obtaining a high optical performance. In particular, one of the aspects of the present invention is to provide a semiconductor optical device including a beam waveguide extending in a longitudinal direction between a pair of end surfaces. The beam waveguide includes an active layer of a quantum well structure having at least one well and barrier layers, and a pair of cladding layers sandwiching the active layer. The active layer has a first and second regions in the longitudinal direction, formed so as to have a photon density in the first region greater than that of the second region. The first region has a differential gain greater than that of the second region so that a variation of refractive index across the beam waveguide is reduced.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuhisa Takagi
  • Publication number: 20030189387
    Abstract: The invention provides a stator for a dynamo-electric machine capable of preventing deterioration of efficiency. In the stator for dynamo-electric machine of which rotor is disposed inside the stator, a stator core 11 comprises: an inside ring core 9 formed annularly by laminating plate-type magnetic members in which a plurality of teeth are provided on one side of a yoke portion, disposing coils 8 in slots each formed between the teeth, bending the plate-type magnetic members so that the coils 8 are located inside, and bringing two end faces into contact with each other; and an outside ring core 10, being made of magnetic members and formed cylindrical in shape, which is fitted on outside of the inside ring 9 and holds the inside ring core 9.
    Type: Application
    Filed: March 4, 2003
    Publication date: October 9, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yuuji Nakahara, Naohiro Oketani, Katsumi Adachi, Akira Morishita, Hiroshi Matsui, Tsuyoshi Takahashi, Takushi Takizawa, Yoshihito Asao
  • Publication number: 20030189853
    Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.
    Type: Application
    Filed: October 1, 2002
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Takaharu Tsuji, Tsukasa Ooishi
  • Publication number: 20030189692
    Abstract: A DMD chip has a substrate, micro-mirrors disposed on the substrate, and a glass cover plate disposed over the micro-mirrors. Each micro-mirror is inclined by +10 degrees or −10 degrees with respect to the substrate to be set to an on-state or an off-state. Incident light produced in a lighting source system is totally reflected in a TIR prism and are incident on the micro-mirrors through the glass cover plate. Outgoing light reflected on micro-mirrors set to the on-state passes through a projection lens and are projected onto a screen to form an image on the screen. Also, outgoing light reflected on micro-mirrors set to the off-state passes out of the projection lens. The glass cover plate is inclined not to be parallel to the substrate. Therefore, light specularly reflected on a surface of the glass cover plate passes out of the projection lens.
    Type: Application
    Filed: October 9, 2002
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Kawano, Junichi Nishimae, Tatsuki Okamoto, Yukio Satou, Atsuhiro Sono
  • Publication number: 20030189263
    Abstract: A semiconductor module is provided with a module substrate, a plurality of semiconductor chips formed on the module substrate, and a mold resin formed so as to integrally cover the plurality of semiconductor chips. Then, a plurality of trenches is formed on the main surface of the module substrate, so as to be parallel to one side forming the main surface, on the side on which the bare chips are formed. Thereby, a semiconductor module can be obtained wherein it is possible to restrict separation of the mold resin from the module substrate.
    Type: Application
    Filed: September 18, 2002
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha; Mitsubishi Electric Engineering Company Limited
    Inventors: Seiji Sawada, Hiroyuki Nakao, Tatsuji Kobayashi
  • Publication number: 20030190828
    Abstract: A connector enabling wiping operation without changing the distance between a male connector and a female connector and capable of changing connectional association by mechanically operating the connector is obtained. The connector comprises a male connector having a male connector terminal, a female connector having a female connector terminal, a relay connector terminal movably mounted on either a male connector body or a female connector body and a drive mechanism part bringing the relay connector terminal into contact with both of the male connector terminal and the female connector terminal and performing rubbing.
    Type: Application
    Filed: December 20, 2002
    Publication date: October 9, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Hiroshi Nakagawa, Naoyuki Shinonaga, Daisuke Ito
  • Publication number: 20030189854
    Abstract: An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.
    Type: Application
    Filed: October 9, 2002
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukiko Maruyama, Takashi Itou
  • Publication number: 20030189224
    Abstract: A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (<S1), respectively. The wire widths W1 and W2 and the wiring spaces S1 and S2 are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S1 is determined also so as to satisfy {S1/P≧0.6}. Further, the signal wires 1 and the ground/power wires 2 have the same wire thickness of a wire thickness T1 which allows an aspect ratio (T1/W1) to be equal to, or higher than, 2.
    Type: Application
    Filed: October 2, 2002
    Publication date: October 9, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Akihiko Ohsaki, Masahiko Fujisawa, Noboru Morimoto
  • Patent number: 6631174
    Abstract: A transmitting side periodically inserts a known signal consisting of successive NP symbols into an information signal consisting of (NF−NP) symbols and transmits the NF symbol signal. The receiving side receives the NF symbol signal, and automatically controls a frequency by estimating a frequency deviation from the incoming signal. More specifically, the receiving side outputs I and Q-channel analog baseband signals from the received incoming signal as well as from a sinusoidal signal outputted from an oscillator, and converts the analog baseband signals to the digital baseband signals. Then a phase difference for one symbol cycle is estimated from the digital baseband signals, integration processing is executed by iterative addition of the estimated values, and the frequency deviation is eliminated from the digital baseband signals using a result of the processing for integration.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Asahara, Toshiharu Kojima
  • Patent number: 6630629
    Abstract: Signal wirings 22, 23 are formed on a pair of substrates 20, 21, and the substrates are joined together through an insulating layer 24 so that the signal wirings 22, 23 are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings 22, 23 are made smooth, and the roughness of the same surfaces is smaller than the skin depth &dgr;s due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: October 7, 2003
    Assignees: Sanyo Electric Co., Ltd., Oki Electric Industry Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 6631475
    Abstract: A microcomputer has an electric potential control unit, a signal generation unit, and a timing signal generation circuit. The electric potential control unit includes a transistor which controls an electric potential of an input terminal which is energized by a power supply. The signal generation unit includes an input buffer circuit which receives a change in the electric potential of the input terminal and supplies an interrupt signal to a CPU. The timing signal generation circuit generates a timing signal which controls conductivity of a transistor and operates the transistor intermittently. A capacitor is connected to the input terminal.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventors: Hiroyuki Nagayama, Hironari Yoshida
  • Patent number: 6631467
    Abstract: A microcomputer has an internal reset signal generator for generating an internal reset signal from an external reset signal supplied via a chip reset input terminal. The internal reset signal generator includes a first two-input logic circuit that has its first gate input terminal connected to the chip reset input terminal and outputs a low-level first logic signal only when its two gate input terminals are placed at a high level. The first logic signal is inverted by an inverter and is supplied to the second gate input terminal of the first two-input logic circuit. The second gate input terminal is pulled up by a capacitor connected to a higher power supply voltage terminal. The external reset signal and the first logic signal are supplied to a second two-input logic circuit that changes the level of the reset signal only when both the inputs are at the high level.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Taiyuu Miyamoto
  • Patent number: 6630757
    Abstract: An elevator hoist apparatus including a ventilation passage within a motor frame includes an inlet suction port at one end, a flow passage extending through the motor, and upper and lower discharge ports at the lower end of the motor frame. The upper discharge port is at a position above the horizontal plane that includes the motor axis. The upper discharge port has an axis forming an angle of 45 degrees with the horizontal plane, and the lower discharge port is at a position below the horizontal plane. A blower is connected to each discharge port, thereby generating a substantially uniform flow of cooling air within the motor frame. Therefore, the flow of cooling air generated within the motor frame is substantially uniform, eliminating stagnation regions and uneven cooling, improving the cooling efficiency.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuaki Nakamura, Hukami Aoki
  • Patent number: 6630821
    Abstract: A magnetic detection device capable of detecting moving direction of a toothed magnetic movement body is provided. The magnetic detection device comprises a circuit for converting output signals of plural magneto-resistance effect elements 21 and 22 located in moving direction of toothed magnetic movable body to a ternary signal of a high level, a low level 1 and a low level 2, and in which a binary signal of the high level and the low level 1 is output when the toothed magnetic movement body is rotated in forward direction and a binary signal of the high level and the low level 2 is output when the toothed magnetic movement body is rotated in reverse direction.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Izuru Shinjo, Hiroshi Sakanoue, Naoki Hiraoka
  • Patent number: 6631092
    Abstract: The DRAM includes a power supply switching circuit which provides a word line select circuit with a power supply potential when a test signal is activated. The potential of a main word line becomes an H level equal to the power supply potential when a word line is not selected. Thus, when a sub-decode signal attains an H level equal to a boosted potential, not only an N channel MOS transistor but also a P channel MOS transistor turn on in a word line driver, and a leakage current running through the word line driver comes to flow. Accordingly, large stress is imposed on the P channel MOS transistor.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kyoji Yamasaki
  • Patent number: 6630705
    Abstract: A semiconductor device and a method of manufacturing thereof can be gained wherein the occurrence of defects can be prevented and it is possible to reduce the manufacturing cost. The semiconductor device includes a capacitor electrode, an insulating layer and a wiring layer. The capacitor electrode is formed on the semiconductor substrate. The insulating film which is formed on the capacitor electrode has a trench which exposes part of the capacitor electrode and has an upper surface. The wiring layer fills in the inside of the trench, has an upper surface and is connected with the capacitor electrode. The upper surface of the wiring layer is located on approximately the same plane as the upper surface of the insulating film.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Maeda, Toshiyuki Oashi, Takashi Uehara
  • Patent number: 6631217
    Abstract: An image processor includes unit pixel circuits, each circuit outputting a pixel value, according to incident light, to an output line; and read circuits in each row and each column, each of which can read out a pixel value of each unit pixel circuit and a result of computing for projection for each row and each column. The unit pixel circuits of each row and column and the corresponding read circuits are connected to each other by discrete output lines. The result of computing for projection readout by the compression processing is an average of pixel values in the unit pixel circuits of each row and of each column.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eiichi Funatsu, Souichiro Kuramochi
  • Patent number: 6630641
    Abstract: An electric discharge machining apparatus includes a wire electrode for machining a workpiece, and a first voltage applying unit for applying a voltage pulse. The voltage pulse has a rise time longer than a discharge formative time lag when a rectangular voltage pulse is applied, when a distance between the workpiece and the wire is an average value in machining, and rises to the same voltage as the rectangular voltage pulse.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taichiro Tamida, Takashi Hashimoto, Akihiro Suzuki, Akihiko Iwata, Atsushi Taneda
  • Patent number: 6629362
    Abstract: The present invention is provided to prevent a rise of temperature of a heating element and temperature of a board by inserting a graphite sheet 1 having high thermal conductivity to a circuit print board without electrically connecting with a conductive hole 6. In order to accomplish the above object, a manufacturing method of a circuit print board according the present invention has a thermal diffusive sheet forming step for forming the thermal diffusive sheet 7 by bonding resin 2 to a graphite sheet 1. Next, the method has a through hole making step for making the through hole on the thermal diffusive sheet and an insulator bonding step for forming a core 10 by thermally pressing the insulator to the thermal diffusive sheet having the through hole 3. Through these steps, the graphite sheet 1 can be inserted into the circuit print board without electrically connecting with the conductive hole 6.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Kobayashi, Seiji Oka, Kazuo Funahashi, Hideki Tsuruse
  • Patent number: 6630815
    Abstract: A battery protective circuit which can ensure the safety and reliability of a rechargeable secondary battery is provided. Personal digital assistants include a main circuit (30) and a battery block (60). The battery block (60) includes a battery (20) and a current-amount control circuit (50). The battery (20) is charged via an AC adapter. The current-amount control circuit (50) includes a current and temperature detecting circuit (for example a PTC element) operative to reduce a current amount when an amount of current flowing in the battery (20) approaches a boundary value of a charge-guaranteed region in which the battery (20) is rechargeable.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: October 7, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kiyoshi Hanafusa, Hiroichi Ishida