Abstract: A task instructing method for use with a work slip issuing terminal 12 and work terminals 14 is provided. The work slip issuing terminal 12 includes a reader/writer 121 which is connected to a central managing apparatus 10 storing task detail update information and which writes and reads information to and from a rewritable print indication area of a card type storage medium. Each of the work terminals 14 also includes a reader/writer connected to the central managing apparatus 10. The method comprises the steps of: causing the work slip issuing terminal 12 to print task details retrieved from the central managing apparatus 10 onto the card type storage medium that is issued as a work slip 20; and causing the work terminal 14, given the work slip 20, to search the central managing apparatus 10 for task detail update information so that the retrieved information is printed on the work slip 20.

Abstract: A dynamic bandwidth assignment system includes a network unit for carrying out cell slot assignment, and a network termination for transmitting cells to the network unit by means of cell slots assigned by the network unit. When the number of consecutive valid cells the network unit receives from the network terminations exceeds a predetermined threshold value, the network unit increases the number of the cell slots to be assigned to the network termination. The system can solve a problem of a conventional system in that it is unavoidable that a cell transfer delay and a bursting tendency of cells are statistically increased.

Abstract: When there is an error in setting of a companding law of an encoder or a decoder, there is a problem of an error in judgment although it should be originally judged that the continuity of the testing channel does not exist.

Abstract: Following data writing into a memory cell array according to an internal address signal, the data read out from each memory cell is compared with expected value data in a readout operation. An associated memory cell array and a test block are provided corresponding to each sub memory cell array. Each test block includes a replacement determination unit for respective combinations of a sequence to replace a memory cell row and a memory cell column in order. Each replacement determination unit writes a defective address only when a defective memory cell having an address differing from the row and column addresses of a defective memory cell already stored is found.

Abstract: An exhaust gas recirculation valve device is provided with a motor shaft, a stepping motor main body driving the motor shaft, a valve shaft having a tip functioning as a proximal end which faces one end of the motor shaft and a distal end provided with a valve, a spring pushing the valve shaft in a closing direction, and a spring holder retaining the spring. In the case that the valve is closed, the tip of the valve shaft and the spring holder are caulked together at a distance between the tip of the valve shaft and the one end of the motor shaft so that a distance between the facing ends of the motor shaft and the valve shaft is equivalent to a difference between a stroke of the motor shaft of the stepping motor main body and a stroke of the valve on opening.

Abstract: An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.

Abstract: A memory cell power supply line is provided to supply a ground potential corresponding to each column in a regular memory cell array. Among fuse elements, the fuse element corresponding to the memory cell column that is to be subjected to redundancy replacement is decoupled, whereby supply of the ground potential to the regular memory cell column to be replaced is suppressed.

Abstract: In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.

Abstract: A memory core part includes a program part and a voltage supply part. The program part includes a program structure part, a latch part and an address compare part. The program structure part includes an electric fuse blown with a program voltage. The voltage supply part supplies the program voltage to the program part every repair address. The latch part holds the program state in the program structure part on the basis of a transfer signal. The address compare part outputs a spare determination result on the basis of an input address and the latched program state.

Abstract: A hotplug tolerant I/O circuit, which is incorporated in a first device, includes a voltage generator. In a hotplug mode, in which an input signal higher than the power supply voltage is applied from a second device to the first device while the power supply voltage is not applied to the first device, the voltage generator generates a control voltage from the input signal, and supplies it to a transistor in the hotplug tolerant I/O circuit. This makes it possible to solve a problem of a conventional hotplug tolerant I/O circuit in that the transistors in the I/O circuit can be damaged in the hotplug mode.

Abstract: The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.

Abstract: Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts the number of pulses of the clock CLK1A based on the clock CLK2B and outputs an error signal ERR1. The clock comparator (16) counts the number of pulses of the clock CLK2B based on the clock CLK1B and outputs an error signal ERR2. An abnormal clock is detected by examining states of the error signals ERR1 and ERR2.

Abstract: The pattern of a spatial frequency filter including a liquid crystal element (1031-103n) is controlled without removing the filter from a projection lens system. Specifically, a spatial frequency filter (103) is disposed at the pupil surface in a projection lens system (10). A means for controlling the spatial frequency filter (103) includes a liquid crystal element controller (15b) and a filter information storage (16b). A pattern required for the spatial frequency filter (103) is transferred from the filter information storage (16b) to the liquid crystal controller (15b). The transmittance and phase shift of the spatial frequency filter (103) are previously designed by simulation, for example. Based on these data, an aspect of applying a voltage to the liquid crystal element (1031-103n) is stored in the filter information storage (16b).

Abstract: First and second memory cell arrays have their respective sides with first and second center circuit bands adjacent thereto, respectively, and provided therein with their respective address latch circuits, row predecode circuits and row decoders. The first and second memory cell arrays share a sense amplifier band having a side with a center cross circuit band adjacent thereto and provided therein with a column decode circuit and a sense amplifier control circuit controlling activating a sense amplifier. As such the number of signal lines between the second center circuit band and the center cross circuit band can be reduced to alleviate thick density of signal lines. Thus there can be provided a DRAM core with readily changeable memory capacity.

Abstract: A forward mesa ridge-embedded semiconductor laser device provides a high power output and includes a base portion of a forward mesa ridge having a narrow width to stabilize transverse mode oscillation and an upper cladding layer having a thickness sufficient to reduce loss of the laser beam, a top portion of the forward mesa ridge being interposed between parts of the current blocking layer to reduce the device resistance. The upper cladding layer includes a first cladding layer having the forward mesa ridge and a second cladding layer opposite the first cladding layer. The second cladding layer is deposited over the first cladding layer through the forward mesa ridge and a current blocking layer is positioned on both sides of the forward mesa ridge.

Abstract: To secure sufficient attractive force against a plunger, an overrunning clutch is arranged so that one end of a thrust spline is positioned so as to maintain a prescribed interval from the end of the plunger in the condition where the plunger is unexcited by an exciting coil and the outside periphery of the output shaft corresponding to the prescribed interval is covered by a cylinder body formed of a non-magnetic material or less permeable material.

Abstract: Position droops produced in main and auxiliary servo motors when main and auxiliary spindles are coupled to each other through a workpiece are obtained by adders, respectively, a difference between those position droops is obtained by a comparator before coupling, a divider divides the position droop difference by the speed of the auxiliary servo motor at the time of detecting the position droop to obtain a position droop difference per a unit speed. Then, after both the spindles are coupled to each other, a multiplier multiplies the position droop difference by the present speed of the auxiliary servo motor, and the adder adds that value to the position command to the auxiliary servo motor. With the above structure, even if coupling is made through the workpiece and synchronization drive is made, an excessive torque can be prevented from occurring, an influence of a change of the change gear ratio with a time is eliminated and a displacement occurring at the time of coupling is corrected.

Abstract: In an optical disk storing digital image information in the form of a succession of blocks, each comprising a plurality of frames comprising I-, P- and B-pictures, wherein an address format is preformatted in front of the block of image information of said plurality of frames, and the data arrangement within each image information blocks is such that I- and P-pictures are collectively disposed. The position of the I-pictures within each block is shifted from one block to another. The I-picture data may be divided into fraction according to the position on the screen, the DCT frequency, or layering, and the fractional I-picture data may be arranged in the image information blocks, and a header or parity signal is recorded in front of each fractional I-picture data. With such a configuration, it is possible to increase the speed of fast playback, and realize smooth playback picture.

Abstract: The vane type hydraulic actuator according to the present invention comprises a guide locking mechanism (guide stopper pin) (1) for guiding the rotor (44) to a locking position where the rotor (44) can be locked to the case (43), and a retaining locking mechanism (retaining stopper pin) (4) for retaining the rotor (44) to the case (43), after the rotor (44) is guided to the locking position. The actuator having vanes, wherein the length in the peripheral direction of the tip portion of the vane having the locking mechanism is substantially identical to that of the vane which is located symmetrically thereto. The length in the peripheral direction of the tip portion of the other vanes is shorter than that of the vane having the locking mechanism.

Abstract: A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.