Abstract: In automatic test equipment (ATE), the current state of all configurable hardware components is maintained in one or more status registers. A configuration interface operates between the ATE test program and the hardware components. The test program issues instructions for configuring the hardware components to the configuration interface, which considers the current configuration status of each hardware component stored in the status registers. When a hardware component is instructed to assume a specific configuration for a given task, the configuration interface compares the target configuration with the current configuration status and forwards the instruction only if they are different, i.e., if the current hardware configuration must be updated. The associated wait times for instructions issued where the target configuration matches the current configuration status are avoided, decreasing setup time.

Abstract: A system for impedance matched switching of an input signal from an input source includes a first switch, such as an FET, for controllably switching the input signal from an input terminal connected to the input source to an output terminal, the switching being controlled according to a control voltage. The system further includes a second switch, such as an FET, for controllably switching a matching impedance between the input terminal and ground according to the control voltage. When the input signal is prevented from passing from the input terminal to the output terminal by the first switch, the input signal passes through the matching impedance, which has an impedance characteristic substantially matched to an impedance characteristic of the input source.

Abstract: In automatic test equipment (ATE), the current state of all configurable hardware components is maintained in one or more status registers. A configuration interface operates between the ATE test program and the hardware components. The test program issues instructions for configuring the hardware components to the configuration interface, which considers the current configuration status of each hardware component stored in the status registers. When a hardware component is instructed to assume a specific configuration for a given task, the configuration interface compares the target configuration with the current configuration status and forwards the instruction only if they are different, i.e., if the current hardware configuration must be updated. The associated wait times for instructions issued where the target configuration matches the current configuration status are avoided, decreasing setup time.

Abstract: A current-mode D/A converter is described having variable output and offset control. According to an exemplary embodiment, a first D/A converter includes a number of first control inputs and an output capable of generating a first current proportional to a number of active first control inputs. A driver includes an input connected to the output of the first D/A converter, a number of second control inputs, and an output capable of generating a second current proportional to the first current based on a number of active second control inputs. A second D/A converter includes a number of third control inputs and an output capable of generating a third current proportional to a number of active third control inputs. Offset control circuitry includes an input connected to the output of the second D/A converter, an offset control input, and an output connected to the output of the driver.

Abstract: A system for impedance matched switching of an input signal from an input source includes a first means, such as an FET, for controllably switching the input signal from an input terminal connected to the input source to an output terminal, the switching being controlled according to a control voltage. The system further includes a second means, such as an FET, for controllably switching a matching impedance between the input terminal and ground according to the control voltage. When the input signal is prevented from passing from the input terminal to the output terminal by the first means for controllably switching, the input signal passes through the matching impedance, which has an impedance characteristic substantially matched to an impedance characteristic of the input source.

Abstract: A method and apparatus are described for adaptively removing interference from a signal. A received signal is amplified linearly along a first signal path to provide a first signal and amplified nonlinearly along a second signal path to provide a second signal. The received signal propagates through the first and second signal paths at substantially the same time. The first and second amplified signals are mixed in proportion according to determined first and second weights, respectively, to provide an output signal having interference removed. The output signal is filtered to produce a first filtered signal corresponding to a ripple envelope of the output signal and filtered substantially simultaneously to produce a second filtered signal corresponding to an average peak detected value of the output signal. The first and second filtered signals are compared to produce an error signal. The first and second weights are determined according to the error signal.

Abstract: A method and system are described for monitoring a deliverable radio frequency (RF) power of an amplifier operable on a monolithic microwave integrated circuit (MMIC). According to an exemplary embodiment, circuitry is configured to capture, on the MMIC, a first portion of an RF signal transmitted from the amplifier to a load, and a second portion of the RF signal reflected from the load back to the amplifier. Circuitry is also configured to generate, on the MMIC, a first signal proportional to an RF power of the first portion of the RF signal, and a second signal proportional to an RF power of the second portion of the RF signal. Additional circuitry is configured to subtract a first reference signal from the first signal to produce a third signal, and a second reference signal from the second signal to produce a fourth signal. Finally, circuitry is configured to subtract the fourth signal from the third signal to produce an output signal proportional to the deliverable RF power of the amplifier to the load.

Abstract: A self-adjusting path is created by utilizing a phase detector and modifying a clock path and a data path to enable the passing of data in either phase of the clock. The new input path is controlled by the output of the phase detector. Each time a command is issued, the phase of the clock is detected and latched. The phase of the clock at the time the command issues is thus captured and can propagate through the pipeline along with the data. Accordingly, each stage along the data path can be synchronized to a different phase of the clock to reduce data corruption.

Abstract: Shorts are detected in terminals fed current by a driver connected to the terminals. To detect terminal-to-ground shorts, at least one virtual driver is connected to the driver for processing an output of the driver, and a detector detects if a short has occurred, based on an output of the virtual driver, by detecting when an output of the virtual driver exceeds a first threshold. If the detector detects that the output of the virtual driver has exceeded the first threshold, this indicates a terminal-to-ground short. To detect terminal-to-terminals shorts, a detector detects when an output of the driver drops below a second threshold. If the detector detects that the output of the driver has dropped below the second threshold, this indicates a terminal-to-terminal short. Shorts may be detected in terminals in one or more write heads. The driver, virtual driver, and detector may be included in a preamplifier.

Abstract: An arrangement for reading data from a magnetic data carrier using a magneto-resistive (MR) head. A bias current source supplies the MR head with a bias current adjustable after MR head change. A bias current control signal having multiple control bits is used for adjusting the bias current. A noise shunting capacitor is connected to the MR head for reducing noise caused by the bias current. A discharging circuit is coupled to the noise shunting capacitor to discharge the capacitor when the bias current is being adjusted, in order to reduce bias current settling time. The discharging circuit comprises a pair of switches for each control bit of the bias current control signal. One of the switches is connected to a positive plate of the noise shunting capacitor, and another switch is coupled to a negative plate of the capacitor. The switches are controlled by a one-shot multivibrator triggered by a falling edge of the corresponding control bit.

Abstract: The stages of a multistage amplifier are quickly switched between operational modes, e.g., from a standby mode to an active mode. The delivery of a control signal to each individual stage is delayed so that the modes of the stages are switched, in a desired sequence. The final amplifier stage is isolated from the operational mode switching of the preceding stages by a buffer. For switching the multistage amplifier from the standby mode to the active mode, the stages and the buffer are turned on, in a desired sequence, beginning with the first stage. For switching the multistage amplifier from the active mode to the standby mode, the stages and the buffer are turned off, in a desired sequence, beginning with the buffer. A delay unit includes a plurality of delay units, one connected to each amplifier stage, except the final amplifier stage, and to the buffer.

Abstract: An amplifier output is biased to optimize performance characteristics such as gain and output voltage. A temperature-independent current is subtracted from a temperature-dependent current. The difference is injected at the amplifier output to bias the amplifier output such that performance characteristics are enhanced. An additional amplifier stage may be used to prevent the bandwidth performance of the amplifier from being affected by the current injection.