Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: Charge accumulated at an output node of an output transistor is discharged to the ground through the output transistor as a spike current. To reduce noise of the spike current, a control signal is sent from an output transistor driving circuit set to a low impedance to the output transistor in a first driving stage to quickly turn on the output transistor, a control signal is sent from the output transistor driving circuit set to a high impedance to the output transistor in a second driving stage to output the spike current through the output transistor at a fixed rate, and a control signal is sent from the output transistor driving circuit set to a low impedance to the output transistor in a third driving stage to quickly discharge all the charge. Therefore, a time-current characteristic of the spike current is set almost in a trapezoid shape, and both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered.

Abstract: An internal clock signal, of which a pulse repetition period is half of that of an external clock signal, is produced in a test circuit from the external clock signal and an external clock enabling signal of which a phase is shifted from that of the external clock signal by ¼ of the pulse repetition period of the external clock signal. When an external write command signal set to a low level is received in the test circuit, an internal write command signal, of which a level is risen up in synchronization with a leading edge of the external clock signal, is produced, and a first pre-charge signal, of which a level is risen up in synchronization with a trailing edge of the internal clock signal obtained just after the leading edge of the external clock signal, is produced. Therefore a write recovery time-period equal to ¼ of the pulse repetition period of the external clock signal is obtained from the internal write command signal and the first pre-charge signal.

Abstract: A semiconductor module is provided with a module substrate, a plurality of semiconductor chips formed on the module substrate, and a mold resin formed so as to integrally cover the plurality of semiconductor chips. Then, a plurality of trenches is formed on the main surface of the module substrate, so as to be parallel to one side forming the main surface, on the side on which the bare chips are formed. Thereby, a semiconductor module can be obtained wherein it is possible to restrict separation of the mold resin from the module substrate.

Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Abstract: In a resin molding method for a semiconductor device, the respective cavities of upper and lower mold blocks are faced each other when mold-clamped, and a lead frame, a semiconductor chip connected to the lead frame and a nut, overlapping and provided on a terminal portion of the lead frame, are integrally molded with a seal resin that is injected into the cavities in the mold-clamping condition, and upper and lower sides of the nut are formed to be resin-tight structures by pressure from elastic bodies.

Abstract: In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.

Abstract: A driving circuit includes a voltage converting circuit receiving a block selection signal and converting to a signal of a boosted potential level, and first and second N channel MOS transistors connected in series between the boosted potential and the ground potential. The gate of the first transistor receives the boosted potential, and a potential level at a connection node between the first and second transistors is provided as a signal BLI (i, 0).

Abstract: An acceleration sensor which can improve precision during self-diagnosis operation. The acceleration sensor includes an amplifier circuit which amplifies a detection signal obtained by converting changes in capacitance between a movable electrode and a self-diagnosis electrode into an electric signal to output the amplified signal as a self-diagnosis signal. The amplifier factor of the amplifier circuit during self-diagnosis operation is controlled to be greater than the factor during non-self-diagnosis operation.

Abstract: A read gate of a DRAM core cell includes first and second N channel MOS transistors having gates connected to a pair of bit lines through first and second nodes, respectively, and third and fourth MOS transistors having gates both of which receive a column selecting signal, with gate oxide films of the third and the fourth N channel MOS transistors being formed to be thinner than gate oxide films of the first and the second N channel MOS transistors. It is accordingly possible to lower an amplitude voltage of the column selecting signal, thereby enabling reduction of electric current consumption and speed-up of an operating rate of the DRAM core cell.

Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: A clamping apparatus includes upper and lower platens; one or more tiebars for connecting the platens; an intermediate platen provided between the upper and lower platens for movement relative to and along the tiebars. Upper and lower mold halves are provided on the upper and intermediate platens, respectively. A linkage is provided for connecting the lower and intermediate platens. The linkage includes upper and lower links connected with each other for rotation on an intermediate shaft. The upper and lower links are pivotably supported on first and second shafts fixed on the intermediate and lower platens, respectively. The intermediate shaft is operatively connected with the drive mechanism so that the mechanism transmits a driving force to the linkage, so that the lower platen is moved relative to the intermediate platen. A set of radial needle bearing and thrust bearing is used for at least one of the intermediate, first and second shafts.

Abstract: A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

Abstract: In DRAM, a bit line pair are connected to the respective gates of an N channel MOS transistor pair of a read gate, and a write data line pair are connected to the respective gates of an N channel MOS transistor pair of a write gate. Therefore, since neither of the read data line pair and the write data line pair is directly connected to the bit line pair, no data signal on the bit line pair is destroyed by noise occurring on the data line pair.

Abstract: Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Abstract: In a VDC circuit, a differential amplifier compares a first reference potential with an internal supply potential to generate a control signal according to a result of the comparison. A constant current source transistor receives at its gate a second reference potential supplied through a path different from that of the first reference potential to operate for controlling an operation current value of the differential amplifier. A drive transistor changes conductance between a node for outputting the internal supply potential and a supply potential according to the control signal.

Abstract: An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.

Abstract: A spare data terminal for inputting/outputting spare memory cell data to the outside of a semiconductor memory device and a terminal for inputting/outputting normal memory cell data are provided separately from each other. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. Thus, test time for detecting a defective bit in the semiconductor memory device can be shortened.

Abstract: Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially transferred to transfer control circuit. Transfer control portion converts the serially transferred link information to parallel information, and transfers the parallel information to latch circuits arranged in the core circuit and corresponding to circuits requiring the LT link information. An influence on an interconnection layout by laser trimmable link elements is eliminated.

Abstract: A shallow P well and a deep P well are formed in the surface of a P type semiconductor substrate so as to partially overlap each other and these wells are surrounded by an N well, a deep bottom N type well and a connection N well. The impurity concentration of this overlapping region is higher than the impurity concentration of the P well or of the deep P well and a P+ type region is formed in the surface of the overlapping region. A potential (VBB) different from the ground potential is applied to the P+ type region. The P+ type region is formed in overlapping region and, thereby, the layout of the semiconductor device can be scaled down.