Abstract: A noncontact IC which transmits and receives data to and from a host computer using RF signals has a buffer for storing received data temporarily and a control circuit for controlling operation of the buffer main memory thereof, wherein the control circuit starts processing data stored in the buffer only when no further data is input after a predetermined data receiving time period has elapsed from the latest data input to the buffer.

Abstract: It is an object of the present invention to simultaneously perform input or output of picture signals for a plurality of components. An image data input interface (310) is capable of input of picture signals (Pm) of three components at its maximum. For example, when picture signals (Pm) of three components are inputted, a clock divider (410) supplies a 1/3 divided signal of a clock signal (CLK) to the image data input interface (310) on the basis of a selection signal (SEL). In the image date input interface (310), the picture signals (Pm) of three components are simultaneously inputted in synchronization with the 1/3 divided signal and they are sent out to a discrete cosine transform unit (4) in synchronization with the clock signal (CLK). The component to which the sent picture signals (Pxy) belong sequentially changes for every 8.times.8 picture elements.

Abstract: A port logical level detection circuit ((81)) detects whether a voltage level of a port (15a) is high or low with respect to a plurality of threshold values. A comparison circuit (82) compares a plurality of detected results with data (S22) held by a port latch (40), and outputs a plurality of comparison results. An accident determination signal generating circuit (83) generates an accident determination signal (S56) from the plurality of comparison results outputted from the comparison circuit (82). Thus, it is possible to determine such an accident that the voltage of the port is at a prescribed logical level of an external circuit (16) or at a level in an indefinite area between prescribed logical levels.

Abstract: A semiconductor device having a multi-value memory including an offset ROM and a manufacturing method thereof can be obtained which allows accurate formation of a source/drain region and an offset region. In this semiconductor device, an offset source/drain region is provided so that a side end portion thereof is positioned substantially in flush with a lower end of an external surface of a sidewall insulating film placed on a side surface of a first gate electrode. Consequently, the offset source/drain region can be formed easily in a self-aligned manner by ion implantation using the sidewall insulating film as a mask, thereby forming the offset region accurately in a self-aligned manner.

Abstract: To obtain a display method navigation map intended to lessen the load of control means such as CPU, by quick scroll display. By comparison between preceding judging region (JO) and present judging region (JN), a changing direction of judging region is recognized, and rewriting is processed in advance in a page (display off divided memory region) of a map memory, being out of map display region of a display device. At this time, rewriting is processed by priority in a divided memory region that is high in possibility of move of the own vehicle and that must be written at the earliest opportunity.

Abstract: A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor.

Abstract: A logic simulation device includes an indefinite value generating signal line extracting unit, a propagation deciding unit and a message output unit. The logic simulation device is supplied with circuit connection data of a logic circuit and input signal data employed for simulating the logic circuit. The indefinite value generating signal line extracting unit extracts a signal line which enters a floating state in excess of an allowance time or that causes a collision of logic states as an indefinite value generating signal line. The propagation deciding unit decides whether or not a propagation candidate gate having a propagation input end which is connected with an indefinite value generating signal line is in a state propagating the indefinite value to its output. The propagation deciding unit decides that the indefinite value generating signal line is an error signal line causing an error only when the propagation candidate gate is in a state of propagating the value at the propagation input end.

Abstract: The temperature of the circuit to be verified is evaluated. A simulation executing section (101) executes logic simulation of the circuit to be verified expressed in function block units at function block level. A circuit action extracting section (103) extracts an actin mode of a function block in its process. A total current consumption calculating section (105) calculates the total current consumption which is the current consumed in the entire circuit to be verified, on the basis of the data of current consumption in each action mode and extracted action mode. An average current calculating section (107) calculates the average current which is the average of the total current consumption over the check period, reflecting the thermal characteristic of the circuit to be verified. An allowable temperature judging section (109) calculates the temperature of the circuit to be verified according to this average current, and compares with an allowable current.

Abstract: A switching regulator is composed of digital circuits only. A switching regulator (30) comprises a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver (2). An output terminal (Q) of an RS flip-flop (5) is connected to one input end of the OR gate (6), the output of a timer (40c) is applied to a set terminal (S) of the RS flip-flop (5), and the output of a comparator (4) is applied to a reset terminal (R1) through an OR gate (7). At a non-reverse input end of the comparator (4), a reference voltage (VE) is applied by a D/A convertor (40b), while a feedback voltage (VFB) is applied to a reverse input end. Accordingly, chopping of the switching transistor (1) is done on the basis of a rectangular pulse.

Abstract: A semiconductor integrated circuit includes a first power system element group having an internal circuit for providing an output signal, and a second power system element group for receiving the output signal. An independently activated and deactivated power source potential is supplied to each of the first and second power system groups. In one embodiment of the invention, a fixing circuit maintains the level of the output signal from the internal circuit when the power source input potential to the first group is lowered or turned off. As a result, through currents in the nature of transitional large currents are reduced in the internal circuit elements of the second group.

Abstract: According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

Abstract: In the region filling circuit of this invention, if only the starting position and the end position of the filling region rare supplied from outside, the inversion of bits in the filling area including the starting position and the end position where the whole bits are possibly not the subject of filling can be executed by hardware independently of a CPU, thereby to shorten the filling time and consequently reducing the time when the CPU is occupied during the filling.

Abstract: A watch don timer comprising a reload register 2 and a shift register 3 is disclosed. In the case where an object to be monitored is operating normally, a circuit 43 is supplied with as a reload request signal the rising timing of a monitor signal changing cyclically, which is reloaded from the reload register 2 of the shift, register 3 in synchronism with a reload request signal in accordance with the value of data located in each bit of the shift register 3. Circuits 41, 42 are adapted to detect an abnormal condition in the case where a reload request signal is given in a cycle shorter or longer than a predetermined cycle of reloading. This configuration realizes a watch dog timer with a comparatively small scale of circuit configuration in which the pulse width of the input signal is monitored, the cycle detected and the execution of a plurality of instructions monitored, while at the same time having a programmable width and cycle and a tolerable range thereof.

Abstract: There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.

Abstract: A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.