Abstract: A microcomputer comprises: a flash memory for storing rewriting control F/W and user S/F; a command register for specifying content of rewriting control; a address register to be subjected to rewriting-control; a data register for specifying data to be written; a power-supply pump circuit in the flash memory; and a control signal register for specifying/outputting a control signal to a memory decoder. A CPU of the microcomputer is capable of accessing these four registers to perform writing or reading. A given bit of the control signal register corresponds to a given control signal. A value written to the register becomes a control signal that will be directly supplied to both of the power supply circuit and the memory decoder, in the flash memory, to control them. By rewriting a set value of this control signal register using the rewriting control F/W according to a specified sequence, processing such as “erase” and “program” of the flash memory is performed.

Abstract: A frequency switching method controlled by a microcomputer (74) incorporated in a frequency switching device is capable of halting a timer (81) at a timing at which a pattern of levels of pulse signals supplied from the timer (81) is agreed with a predetermined pattern, of setting a desired frequency to the timer (81), and then of restarting the operation of the timer (81) after a passage of a predetermined time period counted from the above timing in order to generate pulse signals of a desired frequency and outputs them to a pre-driver (73).

Abstract: A microcomputer includes a read only memory (ROM) with ROM areas in a built-in ROM for emulation by a random access memory (RAM) for fine tuning a program to be written into the ROM. The microcomputer further includes RAM areas in a built-in RAM and an assigning unit for assigning at least one RAM area to each of the ROM areas. In the emulation mode, each of the ROM areas can be replaced with a corresponding RAM area.

Abstract: A power regulator including a coil connected to an output of a DC power source for rectifying an AC voltage, a charge-and-discharge capacitor for charging a current supplied from the DC power source through the coil and a backflow preventing diode, a switching device connected to a connection point of the coil and backflow preventing diode in parallel with the DC power source, and a microcomputer for detecting a zero-cross point of the magnetic field energy generated in the coil or the current flowing through the coil, and for bringing the switching device into conduction in response to the detection of the zero-cross point. This makes it possible to solve a problem of a conventional device in that the switching period of the switching device cannot be changed in accordance with variables such as temperature change, errors in circuit constants and the like because switching periods of the switching device are predetermined values.

Abstract: A successive approximation A/D converter which converts an analog signal to a digital signal by carrying out successive A/D conversions of the analog signal. It carries out, for a least significant bit of the digital signal, A/D conversion of the analog signal using a reference voltage corresponding to a previous digital signal obtained as a result of a previous A/D conversion, increments a current digital signal, which is obtained as a result of the latest A/D conversion, when the least significant bit of the current digital signal is “1”, and decrements the current digital signal when the least significant bit is “0”. This makes it possible to solve a problem of a conventional successive approximation A/D converter in that the tracking ability of the digital signal to variations of the analog signal is degraded because of the long update period involved in the increasing number of the bits of the A/D converter, if full bit conversion is carried out.

Abstract: A communication control device has a central processing unit (3), an input data buffer (14), an output data buffer (15), a readout reload register (17), an output reload register (18), and a timer (19) located between an input terminal (1) and an output terminal (2). The timer (19) reads count values stored in both the reload registers (17, 18) alternately, that have already been set by the central processing unit (3) according to a protocol to be processed, and performs a counting operation based on the count values. Communication data items stored in both the data buffers (14, 15) are latched based on a time out output from the timer (19).