Abstract: A multi-port RAM (MPRAM) having a SRAM and a DRAM. A global bus is arranged between the DRAM and the SRAM to provide bi-directional transfer of 256-bit data blocks between the SRAM and the DRAM. Two independent input/output ports are coupled to the SRAM to enable a user to write or read data to or from the SRAM and DRAM. Byte masking is provided for each of the ports to mask bytes of data supplied to the MPRAM. A write-per-bit (WPB) mask register is arranged between the ports and the SRAM to prevent unnecessary bits of input data from being written into the SRAM. A byte write enable (BWE) mask register is arranged between the SRAM and the DRAM to prevent unnecessary bytes of data from being transferred from the SRAM to the DRAM. Each of the mask registers may be loaded with mask data from both of the ports concurrently, or from any one of them.

Abstract: A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.

Abstract: A protocol converter is provided for interfacing a host computer to manufacturing process equipment. Via a parallel input/output interface (PIO), a data acquisition system is coupled to the process equipment to check and activate various process equipment events. A user terminal provides a graphical user interface for controlling and monitoring the protocol converter. A protocol converter (PC) controller that enables the host computer, the data acquisition system and the user interface to exchange messages with the process equipment comprises a protocol conversion server (PCS) for interfacing the PC controller to the host computer, and the process equipment, a user interface server (UIS) for providing interface to the user terminal, and a data acquisition server (DAS) for supporting the PIO. A separate external mailbox is assigned to each of the servers to receive incoming messages from other servers in the PC controller.

Abstract: A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.

Abstract: A peak detector is provided with a comparator and a storage capacitor coupled to the output of the comparator. An analog input signal is supplied via an input capacitor to the inverting input of the comparator. The non-inverting input of the comparator receives an output signal produced by an output buffer arranged in a feedback loop of the comparator. A level shifter is coupled in the feedback loop to dynamically adjust an input signal supplied to the output buffer in accordance with application requirements. The operation of the peak detector is controlled by non-overlapping clock signals supplied to switches at the input and inner feedback loop of the comparator to cancel offset caused by the comparator and output buffer.

Abstract: One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Abstract: A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.

Abstract: A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

Abstract: A memory having a SRAM, a DRAM and two external IO ports is provided. The SRAM has three IO ports for enabling the external IO ports and the DRAM to access each and every memory cell in the DRAM. Each SRAM cell is provided with two IO ports coupled to the external IO ports, and with an IO port for transferring data to and from the DRAM. The triple-port SRAM cell comprises three input data lines coupled to a latching circuit for writing data supplied from the external IO ports and the DRAM, and three output data lines coupled to the latching system for reading stored data to the external IO ports and the DRAM. Three write address lines and three read address lines provide addressing of the SRAM cell for data writing and reading operations performed by the external IO ports and the DRAM. Each SRAM cell may be read concurrently via all three ports to make the most current data stored in the SRAM accessible from any port at any time.

Abstract: An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

Abstract: An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.

Abstract: A multimedia data encoding and decoding system capable of handling various types of data arranged in variable-size blocks. Frames of image, graphics and text data are supplied to a frame buffer. In response to an encoding command from a CPU, an MPEG encoder compresses the data from the frame buffer in accordance with the MPEG compression algorithm, and outputs to a texture buffer a variable-size data block that corresponds to the frame portion to be displayed. The size of the data block is set by the CPU, and may vary from one macroblock to, e.g., 22.times.16 macroblocks (one frame for MPEG-1). An MPEG decoder reads the variable-size data block from the texture buffer, decompresses and supplies it to a graphics engine that manipulates various type of data to create a picture to be displayed at a video monitor.

Abstract: A SRAM storage cell has a NMOS transistor and a PMOS transistor connected with each other between a source of potential and ground. The sources, gates and gate back plates of the transistors are commonly connected and coupled to a storage node. The drain of the NMOS transistor is supplied with the potential, whereas the drain of the PMOS transistor is grounded. A pass NMOS transistor is connected between the storage node and bit and word lines. This storage cell configuration provides considerably reduced area compared to conventional static storage cells.

Abstract: An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main planar surfaces with the second main planar surface parallel to and positioned at a height lower that the first main planar surface. A third planar surface, generally normal to the first and second main planar surfaces, connects the first and second main planar surfaces on the drain region side of the channel region. The source region is formed in a portion of the first main planar surface, and the drain region is formed in the third planar surfaces and portions of the first and second main planar surfaces. Contours of equal ion concentration in the drain region are non-Gaussian and an interface between the channel region and drain region is generally linear beneath the gate electrode adjacent the generally normal third planar surface.

Abstract: An arched gate MOSFET having first and second source/drain regions formed spaced apart on a main surface of the semiconductor substrate, and a gate electrode formed on said main surface of the semiconductor substrate through an insulating film. The gate electrode extends in a first direction between the first and second source/drain regions defining a channel length, and in a second direction, perpendicular to the first direction, defining a channel width. The surface of the semiconductor substrate is arcuate in shape in the channel width direction and the gate electrode conforms to the arcuate shape of the surface of the semiconductor substrate.

Abstract: A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.

Abstract: An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.

Abstract: Micro ROM testing is provided using timing logic and clocks utilized in normal operation of the micro ROM. A PLA in the micro ROM has its output lines coupled to read amplifiers that receive values read from the PLA locations selected by address inputs. The read amplifiers latch the PLA values into timing generators to produce timing signals of various types supplied to a microcontroller associated with the micro ROM. A test signal is supplied to the timing generators to disconnect them from the outputs of the read amplifiers and to establish a scan chain composed of the timing generators connected in series. Non-overlapping clock signals supplied by a system clock of the microcontroller cause the latched PLA values to shift through the timing generators in the scan chain. At a scan output of the last timing generator in the scan chain, the PLA values are observed and compared with the values expected from the selected PLA locations.

Abstract: SIP or ZIP packages are provided with locking elements of snap fasteners, or have package alignment tabs to combine several IC packages into an IC package assembly. Using a DIP printed circuit board socket, a high density DIP module, for example, a high capacity memory chip, is assembled. The leads of the module are inserted into a motherboard that carries the external conductors to be connected with the inner circuits of the package assembly, and soldered to the motherboard. To make the IC package assembly compatible with a conventional DIP socket, a plastic spacer can be provided between the IC packages. A retaining clip may be used to allow the IC package assembly to be repeatedly inserted and removed to and from the socket without the risk of falling apart.

Abstract: A method and apparatus for electroplating a workpiece to achieve a uniform plating thickness includes a cathode rack having a hook from which the workpiece is suspended and spaced apart from a consumable anode. The rack includes a plurality of plates made of the same material as the anode disposed on opposite sides of the rack. The plates direct a portion of the current emanating from the anode away from the workpiece to produce more uniform plating.