Abstract: A pixel electrode and a line for a storage capacitor are sandwiched by first and second protecting films so as to position them in a different plane from a gate electrode and source/drain lines. An insulating film for a storage capacitor and the second protecting film remain at a crossing of the source line and a gate line, but part of them on a TFT is removed, when a pattern of the removal is at least partially deviated from a pattern of a contact hole in the first protecting film directly covering a polycrystalline Si film over the TFT, so that a short-circuit between lines and a breaking of the lines because of a level difference of film layers. Thus, an occurance of failure because of the short-circuit between lines is inhibited, and failure in the lines is reduced by reducing the breaking of the source line and/or the drain line.