Patents Assigned to Miyage National College of Technology
  • Patent number: 4893156
    Abstract: The disclosed MOS FET device has a semiconductor substrate of for instance n-type, on which a drain zone of for instance p-type and a source zone of for instance p-type are formed with a channel zone disposed therebetween. An insulating thin film is disposed on the channel zone and a gate electrode is formed on the insulating film so as to face the channel zone across the film. At least one of drain zone and the source zone has a tapered portion whose diminished edge extends into the channel zone so as to face the other one of the drain and source zones.
    Type: Grant
    Filed: March 7, 1988
    Date of Patent: January 9, 1990
    Assignee: Miyage National College of Technology
    Inventor: Shinji Karasawa