Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.

Abstract: A processor system suitable to provide an interface between networks includes a software programmable processor and a channel processor that receives data from a network and transforms data at commands from the software programmable processor. The channel can execute only a few simple commands, but these commands are sufficient for a wide range of systems. The commands include (1) a command to transmit received data, perhaps skipping some data; and (2) a command to transmit data specified by the command itself rather than the received data. The channel is fast, simple and inexpensive.

Abstract: In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data.

Abstract: In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data.

Abstract: In a network switch, data received on an input connection can be transmitted on one or more output connections. When the switch receives a command to remove an output connection, the switch queues a marker cell in a queue cells to be transmitted on the output connection. The switch removes the connection when the switch reaches the marker cell as the switch traverses the queue to transmit the cells. A separate queue is provided for each input connection. For each input connection, the switch maintains a linked list of data structures each of which identifies an output connection which is to transmit data received on the input connection but for which the corresponding queue does not have data ready to be transmitted. When the queue gets data ready to be transmitted on all the output connections in the linked list, these output connections are moved to another linked list maintained for output connections for which there is a queue having data ready to be transmitted.

Abstract: A method is provided for the implementation of a time-wheel ATM cell scheduler with very large number of queues that can precisely pace any assigned bandwidth described in [i,m] terms (i cells in m cell-times), as long as m/i>=[number of queues]. The method requires only a small, bounded amount of work per physical connection independent of the number of VCs.

Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible a master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffet.

Abstract: A method is provided for the implementation of a fair queuing ATM cell scheduler that can precisely pace virtual channel (VC) traffic by an assigned weight which defines the available bandwidth to be allocated to that VC. The method provides a minimum service rate to each virtual channel on a small, selected time scale, and requires only a small, bounded amount of work per physical connection, independent of the number of VCs.

Abstract: Different units of a system are identified by their device numbers. The device numbers are set during initialization as follows. Each unit has a pin connected to a unique line of the data bus. During initialization, a control unit drives the device number of each unit onto the corresponding line of the data bus. Arbitration cycles proceed in parallel with bus cycles. The above arbitration techniques are suitable to control access to shared resources other than a shared bus.

Abstract: In an ATM switch, an input port number, an input VPI and an input VCI are used to generate a header appended to the cell when the cell is transmitted. The input port number and the input VPI are combined to form a pointer to a look-up table (LUT). The LUT entry contains a first portion of a pointer to an Input Translation Table (ITT). An ITT entry provides sufficient information to generate the header. The LUT entry contains also some or all of the bits of a mask to be applied to the input VCI to obtain a second portion of the pointer to the ITT. The number of the mask bits is variable. All the mask bits are 1. The mask bits are separated from the first portion of the ITT pointer by a 0 bit.

Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffer.

Abstract: In an ATM switch, queue thresholds vary dynamically depending on switch congestion. All the queues are organized in one or more classes. The thresholds for each class depend inversely on the number of cells in all the queues of the class.

Abstract: In the first period of time during arbitration, each unit requesting access to the bus examines two or more MSBs of its priority number, and indicates these bits by signals on the bus. Thus, the units are divided into groups based on two or more MSBs of the units' priority numbers; at the end of the first period of time, the bus identifies one of the groups which wins arbitration over the remaining groups. In a second period of time, the units of the winning group that request access to the bus examine the next bits of their priority numbers, and indicate these bits by signals on the bus. Thus, the units of the winning group are divided into subgroups based on the next bits of the priority numbers. At the end of the second period of time, the bus indicates the winning subgroup. Arbitration proceeds in this way until the winning unit is determined. The winning unit changes its priority to the lowest priority. All the units that had lower priority than the winning unit increase their priorities.

Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible a master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffer.