Abstract: A wireless communication system, in which a redundancy bit is transmitted from a first communication device to a second communication device when the second communication device fails to decode the encoded bits, includes a processor. The processor selects communication patterns that respectively satisfy a requested quality, calculates, for each of the selected communication patterns, a transmission data length that indicates a length of the redundancy bit, calculates, for each of the selected communication patterns, a transmission latency between the first communication device and the second communication device based on the calculated transmission data length, and generates a retransmission parameter corresponding to a communication pattern with lowest transmission latency among the selected communication patterns.

Abstract: A wireless communication device includes a processor. The processor estimates a quality of a received signal that is transmitted from a source device. The processor determines a communication parameter for a next communication transaction based on an evaluation value that indicates a result of subtracting a second value from a first value, the first value being determined based on a coding rate and a data length of a data signal received from the source device, the second value being determined based on the data length, a modulation scheme and a quality of the data signal. The processor reports the communication parameter to the source device.

Abstract: A coding apparatus includes a check matrix, a calculator, a selector, and a synthesizer. The check matrix includes a parity operation matrix including a matrix along a diagonal, a circulant matrix positioned one row and a predetermined number of rows below the diagonal, and an information operation matrix. The calculator sets, in response to an input of a bit sequence of a message, every pattern of initial values to a less-significant bit sequence of parity bits corresponding to the number of the predetermined rows, and calculates parity bit sequences for the respective patterns of the initial values. The selector selects a parity bit sequence corresponding to one of the patterns of initial values when the less-significant bit sequence of the parity bit sequence matches the pattern of initial values. The synthesizer concatenates the selected parity bit sequence to the bit sequence of the message, and outputs the resultant code word.

Abstract: An error correction method of executing error correction for a coded signal using a space coupling LDPC, includes setting a column weight in a column direction of an element matrix that among element matrices of the space coupling LDPC, corresponds to one end side of a bit string of the signal, to be large as a parity check matrix for detecting errors in multiplying the signal.

Abstract: An object of the present invention is to provide the compression device and the expansion device of a complex digital signal, which further raise the compression ratio of the compression digital signal. The compression device of the present invention comprises: first section that acquires a first phase and a second phase, wherein with a complex digital signal being inputted into the complex digital signal compression device, the first phase is a phase, in polar coordinates, which the complex digital signal has, and it is assumed that the complex digital signal inputted into the complex digital signal compression device is expressed as a sum of two complex digital signals with an equal amplitude, phases of which are centered at the first phase and are shifted by a phase that equals to the second phase in the positive and negative direction respectively; and second section that compresses the first phase and the second phase respectively by performing quantization.

Abstract: A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.

Abstract: A low density parity check codes decoder decodes an LDPC code with an arbitrary coding rate by the same configuration. The low density parity check codes decoder enables decoding of an LDPC code constituted by a base matrix of Mbmax rows and Nbmax columns and a permutation matrix as an element of the base matrix. It stores therein Mbmax×Nbmax validity/invalidity flags, shift amounts of valid permutation matrices, a permutation matrix size in a processing target code, and the number of rows of a base matrix in the processing target code, determined depending on a check matrix for the processing target LDPC code, and generates column addresses and a row address to be given to column processing calculation sections and a row processing calculation section that perform calculation in accordance with a BP algorithm by utilizing the stored information, so that it can process an LDPC code for a smaller base matrix than the aforementioned base matrix as well.

Abstract: A Walsh code assigning apparatus includes a retaining unit retaining assignment order information about an order of assignment of the plural Walsh codes such that one Walsh code having a smaller bit length becomes unable to he orthogonally separated as being precedent over another Walsh code having a larger bit length and a controller including a retrieving unit retrieving an idle Walsh code having an assignment request bit length in accordance with the assignment order information retained in the retaining unit, and assigning unit assigning the idle Walsh code, which has been obtained by the retrieving unit, to the spreading code of a last-named communication channel for which the assignment request is issued.