Abstract: A method for performing entropy coding comprising the steps of (A) receiving an input stream and side information and (B) replacing the input stream with an index to a list of a number of valid input streams that satisfy all constraints associated with each specific type of the side information, where the list of the number of valid input streams that satisfy all constraints associated with each specific type of side information is based on an amount of redundancy in a system.

Abstract: A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.

Abstract: A method for performing entropy coding comprising the steps of (A) receiving an input stream and side information, (B) analyzing the side information to determine all constraints associated with the side information and (C) replacing the input stream with an index to a list of the number of valid input streams that satisfy all constraints associated with each specific type of the side information.

Abstract: A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.

Abstract: An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.

Abstract: Multithreaded data- and context-flow processing is achieved by flowing data and context (thread) identification tokens through specialized cores (functional blocks, intellectual property). Each context identification token defines the identity of a context and associated context parameters affecting the processing of the data tokens. Parameter values for different contexts are stored in a distributed manner throughout the cores. Upon a context switch, only the identity of the new context is propagated. The parameter values for the new context are retrieved from the distributed storage locations. Different cores of the system and different pipestages within a core can work simultaneously in different contexts. The described architecture does not require long propagation distances for parameters upon context switches, or that an entire pipeline finish processing in one context before starting processing in another.