Abstract: Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard.

Abstract: Systems and methods for performing phase tracking scheme for an Analog to Digital converter based tuner. In many embodiments, a phase tracking scheme is used that includes a phase locked loop that corrects the phase of the output signals and an amplitude modulation compensator that modulates the amplitude of the output digital signals to compensate for phase noise based upon the received output digital signals.

Abstract: Low jitter clock interpolator circuits in accordance with embodiments of the invention are illustrated. In many embodiments, the low jitter clock interpolator incorporates a time based numerically controlled oscillator (NCO) to generate a clock signal, and different phases of the resulting clock are created using a clock interpolator. Information from the time based NCO and the interpolator is then used to select phases and create an output clock that is jitter free within the precision of the interpolator.

Abstract: Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard.

Abstract: Systems and methods in accordance with embodiments of the invention convert satellite signals to an intermediate frequency signal and selecting modulated digital data within the satellite signals for content decoding. One embodiment includes an optical low noise block converter (LNB) including a digital channelizer switch configured to select at least one content channel from an input signal including a plurality of content channels modulated onto a carrier and to output an optical signal including the selected at least one content channel.

Abstract: Systems and methods in accordance with embodiments of the invention include converting satellite signals to an intermediate frequency signal for content decoding, and selecting modulated digital data within the satellite signals for content decoding using digital signal processing. One embodiment includes a system configured to select at least one content channel from an input signal including a plurality of content channels modulated onto a carrier, the system including: a digital channelizer switch including: a high speed analog to digital converter configured to digitize an intermediate frequency signal; a digital channelizer configured to digitally tune a content channel from the digitized intermediate frequency signal; and a high speed digital to analog converter configured to generate an analog output signal using the content channel digitally tuned from the digitized intermediate frequency signal by the digital channelizer.

Abstract: An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.

Abstract: Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.

Abstract: An apparatus for converting an analog signal to a digital signal comprising a first analog to digital converter for generating a first digital value from an analog value. A second analog to digital converter for generating a second digital value from the analog value. Logic for determining a correction factor for the second digital value based on a difference between the first digital value and the second digital value, wherein the logic updates the correction factor.