Patents Assigned to Modulate, Inc.
  • Patent number: 6562656
    Abstract: The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias and merged vias for the connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), the second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: May 13, 2003
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6455926
    Abstract: A method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: September 24, 2002
    Assignee: Thin Film Module, Inc.
    Inventor: Chung Wen Ho
  • Patent number: 6331447
    Abstract: A new method is provided for mounting high-density flip chip BGA devices. A dielectric layer is first deposited over the first surface of a metal panel. One or more thin film interconnect layers are created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect pattern. The BUM technology allows for the creation of a succession of layers over the thin film layers. The BUM layers can be used for power or ground distribution and for signal or fan-out interconnect. A cavity is etched on the second surface of the metal panel. A laser is used to create openings for flip chip pad contacts. The panel is subdivided into individual substrates. The method of the invention can also be applied to Land Grid Array and Pin Grid Array devices.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: December 18, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6320256
    Abstract: A new method is provided for packaging high-density IC semiconductor devices. A metal substrate is provided, a layer of dielectric is deposited over the first surface of the metal panel. One or more interconnect layers are then created on top of the dielectric layer, the interconnect layers, which can be thin film interconnect layers, are patterned using maskless exposure equipment. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed in the openings in the metal substrate thereby providing points of electrical contact to the second surface of the interconnect substrate. Holes are created in the first surface of the interconnect substrate thereby providing points of electrical contact to the first surface of the interconnect substrate. Bare semiconductor devices and/or packaged semiconductor devices can be attached on one or both sides of the interconnect substrate.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: November 20, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6294477
    Abstract: A new method is provided for high-density thin film interconnect processing. A thin layer of epoxy is deposited over a substrate surface, a via pattern is created in the epoxy layer, the surface of the epoxy is subjected to a process of swell and etch. A metal plating base is formed on the surface of the dielectric using electroless seeding for the metal deposition. A layer of photoresist is deposited over the plating base and is patterned and etched to create the pattern of the interconnect lines. Semi-additive plating of the interconnect pattern is performed to the plating base. The photoresist is removed. The plating base is removed from between the pattern of the interconnect lines using micro etching thereby creating the interconnect lines. A layer of dielectric is deposited over the surface of the created layer of interconnect lines. A via pattern is created in the dielectric layer. The process may be repeated more than once. Electrical contacts are made to the top metal pads through the top vias.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: September 25, 2001
    Assignee: Thin Film Module, Inc.
    Inventors: Chung W. Ho, Ujwal Anant Deshpaude, Chang-Ming Lin
  • Patent number: 6291268
    Abstract: A new method is provided for the testing of complex, high density flip chip packages. A temporary electrical short is provided by a layer of metal for all the interconnect metal lines of the package, vias are created in a surface of the package for the connection of the flip chips to the package. These vias are plated using either copper or copper followed by nickel and gold. The process of plating requires uninterrupted electrical paths between the vias that are being plated and the layer of metal that provides a temporary electrical short. Where this uninterrupted electrical paths is not present, due to problems of poor via creation or problems of opens in the interconnect lines of the package, the vias will be improperly plated and can as a result be readily identified. The metal layer that has provided the common short between all interconnect lines of the package is now patterned and probed for problems of shorts or opens.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: September 18, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6287890
    Abstract: A new method is provided for mounting high-density IC semiconductor devices. A layer of epoxy is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the epoxy layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of epoxy are created where the layer of epoxy is exposed. One or more IC semiconductor die are inserted into the cavities, are electrically connected to the openings that have been created in the layer of epoxy. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: September 11, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung Wen Ho
  • Patent number: 6277672
    Abstract: A new method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: August 21, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung Wen Ho
  • Patent number: 6242279
    Abstract: A new method is provided for creating high-density packages for wire bonded chips. The invention uses a combination of BUM technology and thin film deposition techniques to create the required interface between the contact points of the BGA device and the contact balls of the BGA substrate. Cavities are created on the metal panel substrates for IC chip insertion.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: June 5, 2001
    Assignee: Thin Film Module, Inc.
    Inventors: Chung W. Ho, Anna Litza
  • Patent number: 6221693
    Abstract: A new method is provided for mounting high-density flip chip BGA devices. A dielectric layer is first deposited over the first surface of a metal panel. One or more thin film interconnect layers are created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect pattern. The BUM technology allows for the creation of a succession of layers over the thin film layers. The BUM layers can be used for power or ground distribution and for signal or fan-out interconnect. A cavity is etched on the second surface of the metal panel. A laser is used to create openings for flip chip pad contacts. The panel is subdivided into individual substrates. The method of the invention can also be applied to Land Grid Array and Pin Grid Array devices.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: April 24, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6197614
    Abstract: A new method is provided for packaging high-density IC semiconductor devices. A metal substrate is provided, a layer of dielectric is deposited over the first surface of the metal panel. One or more interconnect layers are then created on top of the dielectric layer, the interconnect layers, which can be thin film interconnect layers, are patterned using maskless exposure equipment. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed in the openings in the metal substrate thereby providing points of electrical contact to the second surface of the interconnect substrate. Holes are created in the first surface of the interconnect substrate thereby providing points of electrical contact to the first surface of the interconnect substrate. Bare semiconductor devices and/or packaged semiconductor devices can be attached on one or both sides of the interconnect substrate.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: March 6, 2001
    Assignee: Thin Film Module, Inc.
    Inventor: Chung W. Ho
  • Patent number: 6087811
    Abstract: A pulsed-output power supply having a high input power factor. The rate at which energy is transferred from a power supply unit (PSU) to an energy storage element such as a capacitor is monitored and adjusted such that the charging rate substantially matches the time interval between output pulses. In this manner, input power to the PSU is smoothed to a substantially constant level, thereby eliminating input power surges traditionally associated with pulsed-output power supplies and providing a high input power factor (PF). In an embodiment of the invention, energy transfer from the PSU to the capacitor is sensed by a current sensor. The period of current flow to the capacitor is compared to the historical or predicted period between capacitor discharge pulses. The rate of energy transfer from the power supply is automatically adjusted to make these two periods approximately equal.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: July 11, 2000
    Assignee: Analog Modules, Inc.
    Inventors: Ian D. Crawford, Charles G. Smith, John P. Sullivan
  • Patent number: 6001871
    Abstract: A method for inhibiting the growth of lentiviruses and Herpetoviridae viruses, including HIV-1 and HSV-1, -2, respectively, in subjects, comprising administering to a subject in need of antiviral therapy a pharmaceutical composition comprising a therapeutically effective amount of a compound of the formula ##STR1## where: R is(i) H, PO.sub.3.sup..dbd., alkyl of 1 to 12 carbon atoms substituted or unsubstituted, straight chain or branched, 0 to 6 double bonds, (CH.sub.2).sub.n morpholine where n=1-4, morpholinomethylphenyl, orthoaminophenyl, orthohydroxyphenyl, (CH.sub.2).sub.n COOR.sub.2 where n=1-4where R.sub.2 is H, an alkalai metal salt, an alkaline earth metal salt, NH.sub.4.sup..dbd., N.sup.+ (R.sub.3).sub.4where R.sub.3 is independently selected from the group consisting of H and alkyl of 1 to 4 carbon atoms, or(ii) COR.sub.1 wherein R.sub.1 is selected from the group consisting of H, (CH.sub.2).sub.n CH.sub.3, where n=0-6, (CH.sub.2).sub.n COOR.sub.2 where n=1-4 and R.sub.2 is previously defined, (CH.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: December 14, 1999
    Assignee: Immune Modulation, Inc.
    Inventors: Emmanuel A. Ojo-Amaize, Joseph I. Okogun
  • Patent number: 5994328
    Abstract: A method for inhibiting the growth of cancer cells ous tumors. The method comprises administering to a subject in need of anticancer or antitumor therapy a pharmaceutical composition comprising a therapeutically effective amount of a compound of the formula ##STR1## where: R is(i) H, PO.sub.3.sup..dbd., alkyl of 1 to 12 carbon atoms substituted or unsubstituted, straight chain or branched, 0 to 6 double bonds, (CH.sub.2).sub.n morpholine where n=1-4, morpholinomethylphenyl, orthoaminophenyl, orthohydroxyphenyl, (CH.sub.2).sub.n COOR.sub.2 where n=1-4where R.sub.2 is H, an alkali metal salt, an alkaline earth metal salt, NH.sub.4.sup.+, N.sup.+ (R.sub.3).sub.4 where R.sub.3 is independently selected from the group consisting of H and alkyl of 1 to 4 carbon atoms, or(ii) COR.sub.1 wherein R.sub.1 is selected from the group consisting of H, (CH.sub.2).sub.n CH.sub.3, where n=0-6, (CH.sub.2).sub.n COOR.sub.2 where n=1-4 and R.sub.2 is previously defined, (CH.sub.2).sub.n N.sup.+ (R.sub.3).sub.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: November 30, 1999
    Assignee: Immune Modulation, Inc.
    Inventors: Emmanuel A. Ojo-Amaize, Vellalore N. Kakkanaiah, Joseph I. Okogun
  • Patent number: 5968912
    Abstract: Methods for inducing immunosuppression in animals which need immunosuppressive treatment involving administration to animals of a therapeutically effective amount of the cyclic AMP agent HE-33 or its nucleoside.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: October 19, 1999
    Assignee: Immune Modulation, Inc.
    Inventor: Emmanuel A. Ojo-Amaize
  • Patent number: 5841555
    Abstract: A method of providing secure identification for an article, including: providing on the article a diffraction grating strip including a pattern of a series of diffraction grating elements, each the diffraction grating element to diffract light, from a light source, in one of at least three selected different planes; serially illuminating the diffraction grating elements, detecting changes in plane of diffracted light as the diffraction grating elements are serially illuminated, and generating first information representative of the changes in plane; storing the first information representative of the changes in plane; subsequently, serially illuminating the diffraction grating elements, detecting changes in plane of diffracted light as the diffraction grating elements are serially illuminated, and generating second information representative of the changes in plane; and then, comparing the first and second information to determine the authenticity or not of the article.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: November 24, 1998
    Assignee: Control Module Inc.
    Inventors: James S. Bianco, David J. Horan
  • Patent number: 5801193
    Abstract: Methods and compounds for inducing immunosuppression in animals which need immunosuppressive treatment involving administration to animals of a therapeutically effective amount of a compound of the following formula ##STR1## where R is H, PO.sub.3.sup.=, alkyl of 1 to 12 carbon atoms substituted or unsubstituted, straight chain or branched, 0 to 6 double bonds, (CH.sub.2).sub.n morpholine where n=1-4, morpholinomethylphenyl, orthoaminophenyl, orthohydroxyphenyl, (CH.sub.2).sub.n COOR.sub.2 where n=1-4where R.sub.2 is H, an alkalai metal salt, an alkaline earth metal salt, NH.sub.4.sup.+, N.sup.+ (R.sub.3).sub.4 where R.sub.3 is independently selected from the group consisting of H and alkyl of 1 to 4 carbon atoms,COR.sub.1 wherein R.sub.1 is selected from the group consisting of H, (CH.sub.2).sub.n CH.sub.3, where n=1-6, (CH.sub.2).sub.n COOR.sub.2 where n=1-4 and R.sub.2 is previously defined, (CH.sub.2).sub.n N.sup.+ (R.sub.3).sub.4 wherein n=1-4, and (CH.sub.2).sub.n SO.sub.3.sup.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: September 1, 1998
    Assignee: Immune Modulation, Inc.
    Inventors: Emmanuel A. Ojo-Amaize, Joseph I. Okogun, Howard B. Cottam
  • Patent number: 5747474
    Abstract: Methods for inducing immunosuppression in animals which need immunosuppressive treatment involving administration to animals of a therapeutically effective amount of the cyclic AMP agent HE-33 or its nucleoside.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: May 5, 1998
    Assignee: Immune Modulation, Inc.
    Inventors: Emmanuel A. Ojo-Amaize, Howard B. Cottam, Ganesh D. Kini
  • Patent number: 5627663
    Abstract: In a preferred embodiment, a method of providing secure identification for an article, including: providing on the article a diffraction grating strip including a pattern of a series of diffraction grating elements, each the diffraction grating element to diffract light, from a light source, in one of at least three selected different planes; serially illuminating the diffraction grating elements, detecting changes in plane of diffracted light as the diffraction grating elements are serially illuminated, and generating first information representative of the changes in plane; storing the first information representative of the changes in plane; subsequently, serially illuminating the diffraction grating elements, detecting changes in plane of diffracted light as the diffraction grating elements are serially illuminated, and generating second information representative of the changes in plane; and then, comparing the first and second information to determine the authenticity or not of the article.
    Type: Grant
    Filed: July 3, 1995
    Date of Patent: May 6, 1997
    Assignee: Control Module Inc.
    Inventors: David J. Horan, James S. Bianco
  • Patent number: 5465176
    Abstract: In a preferred embodiment, a method of producing embossed first and second elongate, edgewise side by side, repeating, optical patterns on a sheet for use in producing secure identification means, the method comprising: continuously embossing the first and second optical patterns on the sheet, such that the first and second patterns repeat at different rates, so that the first pattern will "walk" with respect to the second pattern.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: November 7, 1995
    Assignee: Control Module Inc.
    Inventors: James S. Bianco, David J. Horan