Abstract: A memory system includes a plurality of memory modules, each including at least one memory array. Each memory array has an associated line of sense amplifier latches, wherein each line of sense amplifier latches is activated independently. Each line of sense amplifier latches is capable of caching a row of data from the associated memory array. The capacity of each memory array and the number of memory arrays are selected such that a cache hit rate of over 90 percent is achieved for the memory system.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A single-port multi-bank refresh scheme is used to cut down the number of collisions between memory refresh operations and memory data access operations. A read buffer is used to buffer read data, thereby allowing memory refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time.