Abstract: A synapse element consisting of a smaller number of elements utilizing common semiconductor technology, and a neuron circuit and a neuron device using the synapse elements are provided. The synapse element comprises a transistor set consisting of two MIS transistors connected in series. The first transistor adjusts the effective &bgr;-value of the transistor set so as to correspond to the weight factor &ohgr; via voltage applied to its gate electrode, and the second transistor switches the current according to input voltage to its gate electrode, so that output of the transistor set represents synapse output &ohgr;X. A voltage holding element and a switching element furnished to the gate of the first transistor give the neuron device a learning ability.

Abstract: A synapse element consisting of a smaller number of elements utilizing common semiconductor technology, and a neuron circuit and a neuron device using the synapse elements are provided. The synapse element comprises a transistor set consisting of two MIS transistors connected in series. The first transistor adjusts the effective &bgr;-value of the transistor set so as to correspond to the weight factor &ohgr; via voltage applied to its gate electrode, and the second transistor switches the current according to input voltage to its gate electrode, so that output of the transistor set represents synapse output &ohgr;X. A voltage holding element and a switching element furnished to the gate of the first transistor give the neuron device a learning ability.

Abstract: A threshold element enabling a logical operation with fewer transistors and easy design and setting of an element weight and a threshold value is provided. In a threshold element of the present invention, MIS (Metal Insulator Semiconductor) transistors each passing a drain current upon excitation corresponding to weight &ohgr;i of input Xi obtained from a logical expression Y=Sign(&Sgr;&ohgr;iXi−1) derived from Y=F(Xi) thereof are connected in parallel. A terminal for transmitting an input signal Xi corresponding to each of the transistors is connected to the gate electrode thereof. By this input signal, excitation of each of the transistors is controlled. An output voltage based on a sum of the drain currents from the transistors is compared with a threshold value by a comparing inverter, and a comparison result is output.