Patents Assigned to MONOLITH INC.
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Patent number: 4581592Abstract: An oscillator including an active device (38), a surface acoustic wave resonator (40) connected in a feedback relationship to the active device and an impedance matching circuit is disclosed. The impedance matching circuit in one arrangement is an output impedance matching circuit including an inductor (46) connected in the feedback loop to the output of the active device. In another arrangement, the impedance matching network is an input impedance matching network including an inductor (42) connected in the feedback loop to the input of the active device. In another arrangement of the invention, a varactor diode (60) is connected in the feedback loop and is controlled by a reverse voltage which changes the capacitance of the diode, adjusting the frequency of the oscillator.Type: GrantFiled: May 3, 1983Date of Patent: April 8, 1986Assignee: R F Monolithics, Inc.Inventor: Ralph C. Bennett
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Patent number: 4577168Abstract: An improved notch filter having a single port, surface acoustic wave transducer in parallel with an inductor and forming a first circuit which primarily blocks the signal frequency at all frequencies except the notch frequency at which point the first circuit becomes essentially resistive and at that point is cancelled by a signal from a second circuit in parallel with said first circuit and which is 180.degree. out-of-phase thereby providing a notch filter.Type: GrantFiled: December 3, 1984Date of Patent: March 18, 1986Assignee: R. F. Monolithics, Inc.Inventor: Clinton S. Hartmann
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Patent number: 4572975Abstract: An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal.Type: GrantFiled: April 2, 1984Date of Patent: February 25, 1986Assignee: Precision Monolithics, Inc.Inventor: Derek F. Bowers
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Patent number: 4542349Abstract: A digital control amplifier is provided as a unitary monolithic device to control the transfer function of an analog signal in response to a digital control, such as from a digital computer. A current transfer cell is employed which uses an amplifier circuit having transistors of like polarity, and is capable of both attenuation and greater than unity amplification of an input analog signal. A digital-two-analog converter is integrated into the system and employs a series of current dividers which enables a common reference current to be used for each bit of the converter. A current reference circuit for the converter employs a band gap voltage regulator with a temperature compensation design that varies the control signal applied to the current transfer cell to compensate for temperature-induced variations in the output of the cell.Type: GrantFiled: February 10, 1984Date of Patent: September 17, 1985Assignee: Precision Monolithics, Inc.Inventor: Werner H. Hoeft
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Patent number: 4538115Abstract: A JFET differential amplifier stage in which the gate-drain voltage of each JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias currents. The JFETs are supplied with currents which force their gate-source voltages to at least 0.5 V.sub.p. A second pair of JFETs are cascoded with the first pair and also develop gate-source voltages of at least 0.5 V.sub.p. The gate-source terminals of the second pair are connected in a loop with the source-drain terminals of the first pair, thereby forcing the gate-drain voltages of the first pair to at least V.sub.p, the minimum voltage necessary to hold the first pair in a desired saturated state. A third pair of JFETs is connected to buffer the first pair from capacitances developed at the gates of the second pair without effecting the AC operation of the circuit.Type: GrantFiled: June 15, 1984Date of Patent: August 27, 1985Assignee: Precision Monolithics, Inc.Inventor: James R. Butler
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Patent number: 4503381Abstract: An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.Type: GrantFiled: March 7, 1983Date of Patent: March 5, 1985Assignee: Precision Monolithics, Inc.Inventor: Derek F. Bowers
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Patent number: 4491758Abstract: A surface wave device (10) having substrate with at least a surface layer of piezoelectric material (12) and at least one pair of opposing electrically conducting pads (14 and 16) is disclosed. A first group of at least three electrodes (18, 20 and 22) in a distance (24) of one half wavelength of a preselected operating frequency is disposed on the piezoelectric surface between the opposing pads. At least one of the electrodes is electrically connected to one of the opposing pads and the remaining electrodes are electrically connected to the other opposing pad. The sequence of the three electrodes is unevenly distributed with respect to which of the pads the electrodes are connected to. At least two additional groups of at least three electrodes similar to the first group have sequences of electrodes within each group that is distinct from the other groups.Type: GrantFiled: May 3, 1983Date of Patent: January 1, 1985Assignee: R F Monolithics, Inc.Inventor: Clinton S. Hartmann
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Patent number: 4491757Abstract: A surface wave device includes a substrate (12 in FIG. 7) having a surface layer of piezoelectric material (14), at least one pair of opposing electrically conducting pads (16 and 18) and at least two electrodes (20 and 22) which generate surface waves that vary significantly in strength in a direction transverse to the opposing pads. An ungrounded pad (16) forms an electrode array of parallel segmented electrodes (24), joined by electrically conducting connecting bars (26), having more segmented electrodes near the center of the transverse distance than near the pads. A grounded electrode (22) forms a segmented electrode array having segmented electrodes (44) joined by electrically conducting connecting bars (46) having fewer segmented electrodes near the center of the transverse distance than near the pads.Type: GrantFiled: May 3, 1983Date of Patent: January 1, 1985Assignee: R F Monolithics, Inc.Inventor: Clinton S. Hartmann
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Patent number: 4471321Abstract: An improved input current compensation circuit is provided for a superbeta transistor amplifier. The circuit has a pair of compensation transistors which simulate the amplifier transistors and support a base current which is mirrored back to the amplifier circuit to cancel the input currents thereof. The compensation transistors are supplied with base current by a control transistor. A special voltage control circuit is provided to establish controlled collector-emitter voltages for the compensation transistors independent of the control transistor, thereby decoupling the compensation transistors from the uncertain effects of the control transistor's base-emitter voltage. The control circuit is connected from the collector of one compensation transistor to the emitter of the other, and is provided with primary and secondary current sources to establish a current flow that sets up a desired bias for the control transistor and results in a near exact cancellation of input bias current.Type: GrantFiled: December 17, 1982Date of Patent: September 11, 1984Assignee: Precision Monolithics, Inc.Inventor: Derek F. Bowers
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Patent number: 4454488Abstract: A surface wave resonator device (10) includes a substrate (12) having a surface layer of piezoelectric material (14), first and second reflective grating structures (16 and 18) and a middle grating structure (40). The middle grating structure includes an odd multiple of one-quarter wavelength for the resonant frequency of the first and second reflective grating structures. The surface acoustic wave transmission velocity of the middle grating structure is substantially equal to the surface acoustic wave transmission velocity of the first and second reflective grating structures. One arrangement includes a surface acoustic wave input transducer (52) and a surface acoustic wave output transducer (58).Type: GrantFiled: July 8, 1982Date of Patent: June 12, 1984Assignee: R F Monolithics, Inc.Inventor: Clinton S. Hartmann
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Patent number: 4454413Abstract: A plurality of carriers for integrated circuit devices are each uniquely coded so as to be recognizable by an automatic decoding apparatus. The devices are tested and the test results accurately correlated with the appropriate devices by recording the test results for each device, reading the identification code for each carrier in the same sequence in which the devices are tested, and then correlating the test results with the device identifications. A prior art requirement of maintaining the carriers in the order in which they were tested is eliminated once the carriers have been thus identified. In a preferred embodiment the carrier body is provided with an array of perforations, the transmission of light through each perforation being blocked by a breakable membrane. Each carrier is coded by breaking a selected combination of its membranes to establish a unique binary identification code for each carrier.Type: GrantFiled: February 19, 1982Date of Patent: June 12, 1984Assignee: Precision Monolithics, Inc.Inventor: William D. Morton, Jr.
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Patent number: 4449067Abstract: A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.Type: GrantFiled: August 6, 1981Date of Patent: May 15, 1984Assignee: Precision Monolithics, Inc.Inventor: Yukio Nishikawa
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Patent number: 4403252Abstract: The present invention provides a method and apparatus for scrambling and unscrambling television signals to prevent reception of acceptable signals by an unauthorized television receiver while maintaining the television signal recoverable by an authorized receiver. The present invention can also be used for reducing the necessary carrier signal power of a television transmitter.A transmitter (12) passes a television signal through at least one linear filter (30, 32 and 34) of the type that produces multiple time delayed signals of differing time delays.A receiver (14) receives the multiple time delayed signals from the transmitter and passes them through at least one linear filter (64, 66 and 68) to add the signals together so that one signal representative of the original is reinforced, allowing acceptable reception by an authorized viewer.In one arrangement, the linear filters are SAW devices.Type: GrantFiled: February 26, 1982Date of Patent: September 6, 1983Assignee: R F Monolithics, Inc.Inventors: Lawrence H. Ragan, Clinton S. Hartmann
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Patent number: 4374335Abstract: An I.C. integrator circuit is provided with an active tuneable element by which a precise integrator time constant can be established, despite variations in the values of individual circuit components. A plurality of integrator circuits are connected in an overall frequency responsive circuit, each integrator circuit having a input transconductance stage, an output integrating stage, and an adjustable intermediate conditioning stage, the latter stage preferably comprising a Gilbert multiplier circuit. The time constant of each integrator circuit is controlled by the conditioning stage, which in turn is under the control of a bias circuit common to all of the integrator circuits. A desired net frequency response characteristic can be achieved by simple adjustments to the common bias circuit, despite normal tolerances and variations among individual integrator circuits.Type: GrantFiled: May 19, 1980Date of Patent: February 15, 1983Assignee: Precision Monolithics, Inc.Inventors: Kiyoshi Fukahori, Yukio Nishikawa
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Patent number: 4353046Abstract: A surface wave device is disclosed which includes a substrate (12) having a piezoelectric surface (14), an acoustic surface wave transducer (16 and 18) for converting between an electrical signal and acoustic surface waves propagating on the piezoelectric surface and reflective structures (22) which cause reflections of acoustic surface waves in the portion of the piezoelectric surface over which the transducer is disposed. Numerous kinds of reflective structures are disclosed. An acoustic surface wave resonator using the present invention is disclosed, along with bandpass filters with multiple poles. A low-loss transversal filter using the present invention is also disclosed.Type: GrantFiled: November 4, 1980Date of Patent: October 5, 1982Assignee: R F Monolithics, Inc.Inventor: Clinton S. Hartmann
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Patent number: 4340851Abstract: An improved start-up circuit is provided for self-biased circuits of the type connected to a supply voltage and having biasing currents stable at two operating points at which the biasing currents are either zero or nonzero in value when the supply voltage is nonzero and having sufficient regenerative feedback to raise the level of the biasing currents to the nonzero value when an initial current is provided to the circuit. The start-up circuit includes a resistive element which provides a current path from the supply voltage to the self-biased circuit and a transistor element, responsive to the current flow through the path for supplying an initial current to the self-biased circuit, whereupon the regenerative feedback causes the circuit to draw a current related to the biasing current through the current path as the biasing currents reach the nonzero operating point.Type: GrantFiled: June 18, 1980Date of Patent: July 20, 1982Assignee: Precision Monolithics, Inc.Inventor: Yukio Nishikawa
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Patent number: 4333047Abstract: A current control circuit which can be used to provide starting current during the build-up of an input voltage, and terminate the starting current when the input voltage has reached a predetermined level. The preferred embodiment employs three FETs and one bipolar transistor, located in a total of only two isolation pockets on an integrated circuit chip. The first FET, which is scaled to operate in its saturated region while the second FET is in its resistive region, transmits a current received from the second FET as an output starting current during the initial portion of the input voltage build-up. During this time the second FET holds the gate-source voltage of the first FET to a level less than its pinch-off voltage. The third FET has its gate and source terminals connected in parallel with the first FET, and its drain connected to the base of the bipolar transistor, which is also connected to shunt current away from the first FET when appropriately gated.Type: GrantFiled: April 6, 1981Date of Patent: June 1, 1982Assignee: Precision Monolithics, Inc.Inventor: John A. Flink
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Patent number: 4285051Abstract: An improved analog track and hold circuit has a glitch-free output as the circuit switches between the tracking and the holding of an input analog signal. The circuit is of the type having a capacitor for storing an analog voltage, a transconductance amplifier for producing a charging current for the capacitor proportional to the analog voltage, a current switch for connecting and disconnecting the charging current for the capacitor, and an output circuit to buffer the capacitor voltage to the output. The improvement includes a diode array establishing first and second reference nodes across the capacitor. The diodes in the array clamp the first and second nodes to fixed incremental voltage values greater and lesser, respectively, than the capacitor voltage as the circuit tracks the analog voltage, and to fixed incremental voltage values lesser and greater, respectively, than the capacitor voltage, as the circuit holds the analog voltage.Type: GrantFiled: February 29, 1980Date of Patent: August 18, 1981Assignee: Precision Monolithics, Inc.Inventor: Paul R. Henneuse
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Patent number: 4272656Abstract: An electronic circuit simulates the direct current characteristics of the hybrid transformer portion of the telephone system call-handling equipment. The circuit is connected across a two-wire telephone subscriber loop and supplies a loop current that is proportional to the difference between a constant current and a reference current. The circuit contains a voltage sensing circuit which senses the voltage across the loop and transfers the sensed voltage across a reference resistor, thereby developing a reference current through the resistor which is proportional to the voltage across the subscriber loop. An integral current generator supplies a constant current to the circuit. An integral current subtractor, connected between the output of the voltage sensing circuit and the current generator subtracts the constant current from the reference current. The resulting current forms the input current to an integral current amplifier.Type: GrantFiled: April 5, 1979Date of Patent: June 9, 1981Assignee: Precision Monolithics, Inc.Inventor: Yukio Nishikawa
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Patent number: 4260911Abstract: A junction FET switching circuit and method in which the gate-source voltage of the switching FET is varied with changing temperature so as to maintain the FET channel resistance substantially constant over a selected temperature range. An offset is introduced to the gate-source voltage to permit adequate voltage variation over the temperature range.Type: GrantFiled: February 26, 1979Date of Patent: April 7, 1981Assignee: Precision Monolithics, Inc.Inventors: Paul M. Brown, Jr., Adib R. Hamade