Abstract: A digital signal processor (DSP) circuit is configured to recursively retrieve and process pairs of data points in a symmetric digital filter. The data points are retrieved from an external source (e.g., compact disk) at a first frequency, and processed within the DSP at a second frequency. The DSP employs a floating pointer scheme, which effectively functions a buffer to thereby compensate for jitter or drift between the first and second frequencies.

Abstract: A digital-to-analog converter (DAC) for generating a pulse width modulated (PWM) signal. A dual-DAC implementation includes a read-only memory (ROM) containing a plurality of addressable output signals, respective shift left and shift right registers configured to simultaneously receive an output signal from the ROM, and respective first and second DACs are configured to receive the left shifted output and right shifted output, respectively, from the shift left and shift right registers. Both DAC outputs are applied to an analog summer which generates an output signal indicative of the sum of the outputs from the two DACs.

Abstract: Method and apparatus for implementing a digital filter employing coefficients expressed as sums of 2 to an integer power. Coefficients expressed as sums of powers of 2 may be algebraically manipulated such that higher order terms are replaced by an equivalent group of lower order terms. In the context of a shift-and-add algorithm, the lower order terms require fewer shifting operations and less total hardware to effect multiplication than the corresponding higher order terms.