Patents Assigned to Monolithic 3D Inc.
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Publication number: 20210375972Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.Type: ApplicationFiled: August 14, 2021Publication date: December 2, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20210366921Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.Type: ApplicationFiled: July 4, 2021Publication date: November 25, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han
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Publication number: 20210358794Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a second level including a plurality of second transistors, where the second level overlays the first level, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the plurality of second transistors is at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.Type: ApplicationFiled: July 25, 2021Publication date: November 18, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210357568Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, and the second placement includes placement of the first logic circuit based on the placement of the first memory array.Type: ApplicationFiled: July 26, 2021Publication date: November 18, 2021Applicant: Monolithic 3D IncInventors: Zvi Or-Bach, Zeev Wurman
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Publication number: 20210359122Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at leaType: ApplicationFiled: July 26, 2021Publication date: November 18, 2021Applicant: Monolithic 3D Inc.Inventor: Zvi Or-Bach
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Publication number: 20210351135Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the second level includes at least one voltage regulator.Type: ApplicationFiled: July 25, 2021Publication date: November 11, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20210343570Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210343722Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes at least one scan-chain to support circuit test.Type: ApplicationFiled: July 4, 2021Publication date: November 4, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20210343571Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing additional processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one of the first memory cells is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with the processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Patent number: 11164898Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs), a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.Type: GrantFiled: March 29, 2021Date of Patent: November 2, 2021Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar
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Publication number: 20210335751Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.Type: ApplicationFiled: July 11, 2021Publication date: October 28, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
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Patent number: 11158598Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.Type: GrantFiled: July 11, 2021Date of Patent: October 26, 2021Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
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Publication number: 20210320026Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.Type: ApplicationFiled: June 15, 2021Publication date: October 14, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210313345Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.Type: ApplicationFiled: June 14, 2021Publication date: October 7, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
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Publication number: 20210305063Abstract: A 3D semiconductor device, the device including: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one Electrostatic discharge (ESD) circuit.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
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Publication number: 20210305079Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.Type: ApplicationFiled: June 5, 2021Publication date: September 30, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210296157Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.Type: ApplicationFiled: May 31, 2021Publication date: September 23, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist
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Publication number: 20210294031Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.Type: ApplicationFiled: May 25, 2021Publication date: September 23, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20210296155Abstract: A 3D semiconductor device, the device comprising: a first level comprising a single crystal layer, first transistors and a first metal layer; memory control circuits comprising said first transistors; a second level disposed above said first level, said second level comprising second transistors; a third level disposed above said second level, said third level comprising a plurality of third transistors; wherein said third transistors are aligned to said first transistors with a less than 40 nm alignment error, wherein said second level comprises a plurality of first memory cells, wherein said third level comprises a plurality of second memory cells, wherein one of said second transistors is at least partially self-aligned to at least one of said third transistors, being processed following a same lithography step, wherein at least one of said second memory cells comprises at least one of said third transistors, wherein said memory cells comprise a NAND non-volatile memory type.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar, Zeev Wurman
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Publication number: 20210287941Abstract: A method to process a 3D device, the method including: providing a first wafer including first transistors and a plurality of first interconnecting metal layers; providing a second wafer; processing the second wafer to form second transistors and a plurality of second interconnecting metal layers; processing further the second wafer with a first singulation process providing a plurality of dies; placing the plurality of dies on top of the first wafer; performing a bonding process to simultaneously bond the plurality of dies to the first wafer thus forming a bonded structure; and processing the bonded structure with a second singulation process providing a plurality of bonded dies, where the bonded structure includes oxide to oxide bonding, and where the second singulation process includes an etch process.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Applicant: Monolithic 3D Inc.Inventor: Zvi Or-Bach