Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead.

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

Abstract: A semiconductor memory device (100) utilizing a programming transistor (54) capable of switching high programming currents, and a read transistor (53) capable of sensing the state of the cell (i.e. programmed or unprogrammed). The programming transistor, utilized only when programming the cell, being rather large, is rather slow. The read transistor, utilized only when reading the cell, is constructed to be as small as possible, thereby achieving a substantially increased reading speed over prior art PROM devices which utilize a single transistor per memory cell for both programming and reading.