Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Abstract: A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases exponentially as temperature increases. The temperature-adaptive refresh controller selects the refresh period of the memory cells in response to the subthreshold current of a reference transistor. The subthreshold current of the reference transistor increases exponentially as temperature increases As a result, the refresh period is empirically tied to the data retention time. Consequently, the power required for refresh operations decreases as temperature decreases. Power is therefore conserved in applications that operate predominantly at room temperature.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to perform external accesses during one portion of a clock cycle, and required refresh operations during another portion of the same clock cycle.

Abstract: A non-volatile memory cell fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses only one layer of polysilicon. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) commonly available in a conventional logic process. This non-volatile memory cell can be programmed and erased using relatively low voltages. As a result, the voltages required to program and erase can be provided by transistors readily available in a conventional logic process. The program and erase voltages are precisely controlled to avoid the need for a triple-well process. In one embodiment, the non-volatile memory cells are configured to form a non-volatile memory block that is used in a system-on-a-chip. In this embodiment, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory.

Abstract: A structure and method of controlling data transfer between a memory and a bus. For write operations, a write buffer is coupled between the bus and the memory array. Data that has been transferred into the write buffer is transferred from the write buffer to the memory array at a faster rate than data is transferred from the bus to the write buffer. For read operations, a read buffer is coupled between the bus and the memory array. Data is transferred from the memory array to the read buffer at a faster rate than data is transferred from the read buffer to the bus.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell that includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. After the first set of thermal cycles are complete, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to perform external accesses during one portion of a clock cycle, and required refresh operations during another portion of the same clock cycle.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A method is provided for operating a memory system having a plurality of memory blocks. The method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks when the asserted timing signal is received; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network.

Abstract: A non-volatile memory cell fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses only one layer of polysilicon. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) commonly available in a conventional logic process. This non-volatile memory cell can be programmed and erased using relatively low voltages. As a result, the voltages required to program and erase can be provided by transistors readily available in a conventional logic process. The program and erase voltages are precisely controlled to avoid the need for a triple-well process. In one embodiment, the non-volatile memory cells are configured to form a non-volatile memory block that is used in a system-on-a-chip. In this embodiment, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shall P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A method of operating a system-on-a-chip having a logic circuit and a thin-oxide non-volatile memory embedded or located on a single chip. In this method, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field, while the system-on-a-chip is operated in response to the data stored in the volatile memory. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the non-volatile memory cells are improved.

Abstract: A system for handling refresh of a DRAM array or other memory array requiring periodic refresh, such that the refresh does not require explicit control signaling between the memory array and a memory controller. External accesses and refresh operations are controlled so that the refresh operations do not interfere with the external accesses under any conditions. A multi-bank refresh scheme is used to reduce the number of collisions between external accesses and refresh operations. A read buffer buffers read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of the same memory bank for a long period of time. A write buffer buffers write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a single memory bank for a long period of time. Both the read and write buffers can be constructed of DRAM cells.

Abstract: A four-transistor RAM cell is provided by a pair of cross-coupled driver transistors configured to store a data value, and a pair of access transistors coupled to the driver transistors. The driver transistors and access transistors are sized so the driver transistors are not stronger than the access transistors. In one embodiment, the driver transistors are PMOS transistors and the access transistors are NMOS transistors, with these transistors all having substantially the same size. These PMOS and NMOS transistors are fabricated using a conventional ASIC or logic process. The PMOS transistors are located in an N-well, which is biased at a voltage greater than the VCC supply voltage. The gates of the access transistors are coupled to a word line, and the sources of the access transistors are coupled to a pair of bit lines. The bit lines are coupled a regenerative sense amplifier and a bit line equalization circuit.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.

Abstract: A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines (128) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Abstract: A memory array requiring periodic refresh operations is controlled such that the refresh operations do not require explicit control signaling or handshake communication between the memory array and a memory controller. External accesses and refresh operations are handled such that refresh operations do not interfere with external accesses under any conditions. A multi-bank refresh scheme reduces the number of collisions between refresh operations and external accesses. A read buffer is used to buffer read data, thereby allowing refresh operations to be performed when consecutive read accesses hit the address range of a particular memory bank for a long period of time. A write buffer is used to buffer write data, thereby allowing refresh operations to be performed when consecutive write accesses hit the address range of a particular memory bank for a long period of time. The memory array, read buffer and write buffer can be constructed of DRAM cells.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.