Abstract: A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.

Abstract: A device operable as an interface controller for a defined data bus, wherein the interface controller operates to transfer entire blocks of data, bidirectionally, one byte at a time, while making each byte available as it is received for use by either the computer or by the memory. In addition, the present invention utilizes an interface controller with a single flow-through register, and pluralities of switches, operable in accordance with decoded commands for transferring data in the aforementioned manner in either direction through the same register.