Abstract: In a system having a frequency encoded data stream and a source of clock signals phase locked to the data stream, for subsequent demodulation of the data stream, the clock source is at a frequency that is a multiple of the nominal frequency for demodulating, and a counter is employed to divide the clock. The counter is controlled by the output of a phase comparator, to control the addition to and inhibiting of counting of the counter. The control circuit controls the counter in a non-linear relationship with respect to the phase error, and has a memory function for storing previous states of the counter, to permit repetitive correction for small errors in the same manner. The phase comparator and control are preferably a programmed logic array.

Abstract: A microcomputer board has a first section with fixedly mounted microcomputer components interconnected by a printed circuit, and a second section having unconnected wire-wrap terminals adapted to receive DIP components. Wire-wrap terminals are provided for interconnecting the printed circuit with the wire-wrap section of the board, and additional wire-wrap terminals are provided for I/O connections. A ground plane extends between the wire-wrap connectors, on one side of the board, and voltage planes extend between the wire-wrap terminals on the other side of the board. Wire-wrap terminals may be provided in the wire-wrap section of the board and connected to the voltage and ground planes.