Abstract: Method and apparatus for refreshing DRAM devices (chips) in a computer system. Each DRAM device incorporates circuitry to carry out a burst of RAS cycles during each refresh period. Three different modes are used to trigger the device into refresh. In one mode, each DRAM device incorporates a refresh timer; only one master DRAM device in the system has its refresh timer enabled. The refresh master device generates a refresh request every time the refresh timer times up. A memory controller, after receiving the request, generates an acknowledge signal when certain system conditions are met. All DRAM devices in the system monitor the refresh request and acknowledge handshake continuously. Upon detection of refresh acknowledge, each DRAM device caries out a sequence of predesignated refresh cycles.

Abstract: A multi-port DRAM cell structure that enables read, write and refresh accesses at each port of the DRAM cell. The DRAM cell includes a storage capacitor for storing a data value, and a plurality of ports for accessing the storage capacitor. Each port enables both read and write accesses to the storage capacitor. Each port can include a port access transistor, a port bitline and a port wordline. The port access transistor includes a gate electrode, a source and a drain. The source of the port access transistor is coupled to the storage capacitor, the drain of the port access transistor is coupled to the port bitline, and the gate electrode of the port access transistor is coupled to the port wordline. This cell architecture enables overlapping read and write accesses to be simultaneously performed at the various ports of the multi-port DRAM cell.