Abstract: The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

Abstract: The present disclosure provides multi-channel receiver and multi-channel reception method.

Abstract: A beam generator, a beam generating method, and a chip are provided. The beam generator comprises a first channel, a second channel, and a signal merging module; the first channel comprises a first-channel filter, the first-channel filter is used to filter an input signal to obtain a first filtered signal; the first filtered signal comprises a desired signal; the second channel comprises: a second-channel blocking module, used to block the desired signal in the input signal to obtain a blocked signal; a compensation filter, connected to the second-channel blocking module for compensating for the blocked signal to obtain a second filtered signal; and an adaptive filter connected to the compensation filter for adaptively filtering the second filtered signal to obtain a third filtered signal; the signal merging module is for merging the first filtered signal and the third filtered signal to obtain an output signal.

Abstract: A beam generator, a beam generating method, and a chip are provided. The beam generator comprises a first channel, a second channel, and a signal merging module; the first channel comprises a first-channel filter, the first-channel filter is used to filter an input signal to obtain a first filtered signal; the first filtered signal comprises a desired signal; the second channel comprises: a second-channel blocking module, used to block the desired signal in the input signal to obtain a blocked signal; a compensation filter, connected to the second-channel blocking module for compensating for the blocked signal to obtain a second filtered signal; and an adaptive filter connected to the compensation filter for adaptively filtering the second filtered signal to obtain a third filtered signal; the signal merging module is for merging the first filtered signal and the third filtered signal to obtain an output signal.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Abstract: An image processing method converts an original image represented in an original color gamut to a target image represented in a target color gamut. The image processing method comprises: A) calculating a set of primary color direction deviations between a set of original primary color directions of the original color gamut and a set of target primary color directions of the target color gamut, wherein each of the set of primary color direction deviations corresponds to a primary color; B) determining, for each pixel in the original image, a corrected color coordinate of the pixel based on a set of offsets of an original color coordinate of the pixel in the original color gamut relative to the set of original primary color directions and the set of primary color direction deviations; and C) mapping, for each pixel in the original image, the corrected color coordinate of the pixel into the target color gamut to generate a target color coordinate of the pixel in the target color gamut.

Abstract: The present disclosure provides multi-channel receiver and multi-channel reception method.

Abstract: A video stream protection device is for protecting a video stream to be decoded. The video stream contains one or more data units each having a header section and a body section, and the header section contains header information indicative of a data type of the corresponding body section. The video stream protection device comprises: an identification module for identifying the one or more data units based on respective start positions of the one or more data units; a data type detection module for obtaining the header information of the identified data units, and determining the data type of the body section of each identified data unit based on the header information of the identified data unit; and a control module for determining whether to prohibit decoding of data of each data unit based on the data type of the body section of the data unit.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Abstract: The present application discloses a method of interpolating an image including a pixel array formed of multiple pixels. The method includes: determining a position of an interpolation point relative to the pixel array; determining weights of an edge direction of the pixel array at the position of the interpolation point in a plurality of preset edge directions based on pixel values of a plurality of pixels adjacent to the interpolation point; selecting, for each preset edge direction, one or more corresponding pixel sub-arrays covering the interpolation point from the pixel array to calculate an interpolation pixel value of the interpolation point; calculating a weighted interpolation pixel value of the interpolation point based on the weights of the edge direction of the pixel array at the position of the interpolation point in the preset edge directions and the interpolation pixel value of the interpolation point corresponding to each preset edge direction.

Abstract: The present application relates to the field of integrated circuit design and manufacturing, and discloses a USB transmission device and a transmission method, which may greatly improve the transmission rate when transmitting a large number of small files. The device includes: a configuration module, configured to configure a first transfer ring corresponding to a first transfer thread and a second transfer ring corresponding to a second transfer thread for one endpoint in a memory; a USB host controller, configured to directly perform a transmission of the second transfer thread according to the configured second transfer ring when a transmission of the first transfer thread ends.

Abstract: The present application relates to the field of integrated circuit design and manufacturing, and discloses a USB transmission device and a transmission method, which may greatly improve the transmission rate when transmitting a large number of small files. The device includes: a configuration module, configured to configure a first transfer ring corresponding to a first transfer thread and a second transfer ring corresponding to a second transfer thread for one endpoint in a memory; a USB host controller, configured to directly perform a transmission of the second transfer thread according to the configured second transfer ring when a transmission of the first transfer thread ends.