Abstract: The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.

Abstract: The present disclosure provides a Multiple Inputs Multiple Outputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

Abstract: The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.

Abstract: The present disclosure provides a Multiple Inputs Multiple Ouputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

Abstract: The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.

Abstract: The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.