Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: Processes and apparatuses for direct current (DC) offset cancellation using digital signal processing. Some embodiments of the invention are summarized in this section. In one embodiment, a circuit includes: an analog receiver; and a feedback circuit comprising a digital signal processor coupled with the analog receiver to generate a feedback signal to the analog receiver.

Abstract: Methods and apparatuses for blind equalizers with multiple constant modules. In one embodiment, a circuit, includes: a filter to produce an output based on an input that represents a symbol being received, the symbol being one of a Quadrature Amplitude Modulation (QAM) constellation; a decision engine coupled to the filter to generate a result indicating one region of a plurality of regions in a QAM constellation diagram, the output of the filter being in the indicated region which includes a plurality of symbols of different radii in the constellation diagram; and an error reduction engine coupled to the decision engine and the filter to reduce a difference between a selected one of a plurality of constants and a modulus of the output; where each of the plurality of constants correspond to one of the plurality of regions; and the selected one of the plurality of constants is selected according to the result of the decision engine.

Abstract: Methods and apparatuses for blind equalizers with a hybrid adaptation error. In one embodiment, a Quadrature Amplitude Modulation (QAM) signal receiver, includes: a filter to reduce error in equalization, the filter to output a QAM signal; a decision engine coupled to the filter to determine a symbol based on the QAM signal; a first error generator coupled to the filter to compute a first error signal based on the QAM signal and a constant; a second error generator coupled to the filter and the decision engine to compute a second error signal based on the QAM signal and the determined symbol; an error combinator coupled to the first and second error generators to generate a combined error signal from the first and second error signals; and an adaptation engine coupled with the error combinator and the filter to reduce a equalization error according to the combined error signal.

Abstract: Methods and apparatuses to perform iterative decoding of Low Density Parity Check (LDPC) codes based on selecting a lambda number of minimum values. In one aspect, an LDPC decoder, includes: means for sorting a plurality of incoming messages of a check node according to magnitudes of the incoming messages; means for identifying a predetermined number of unique message magnitudes from the incoming messages; and means for computing outgoing messages for a subset of the plurality of incoming message, where the messages of the subset have different magnitudes larger than the predetermined number of unique message magnitudes but the outgoing messages are computed to have the same magnitude. In at least one embodiment, the decoder further includes means for computing outgoing messages that have magnitudes equal to any of the predetermined number of unique message magnitudes. In general, the magnitudes computed for all outgoing messages may not necessarily be the same.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.

Abstract: Methods and apparatuses to detect spectrum inversion based on estimated frequency offset in carrier signal. In one embodiment, a receiver includes an I/Q swap module to output an in-phase component and a quadrature-phase component; a frequency offset estimator to determine an offset in carry frequency of the in-phase and quadrature-phase components; and a spectrum inversion detector coupled to the frequency offset estimator and the I/Q swap module. The spectrum inversion detector is configured to signal the I/Q swap module to swap the in-phase component and the quadrature-phase component when an absolute value of the offset in carry frequency is above a predetermined threshold.

Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Abstract: High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

Abstract: In one embodiment, a personal television broadcasting system includes one or more television receivers; and a television signal transmitter coupled to one of: a personal computer, a set top box, a game console, and a portable video player to broadcast video content to the one or more television receivers that are limited within a range of a personal area. In one embodiment, a television signal transmitter is integrated with one of: a personal computer, a set top box, a game console, and a portable video player.

Abstract: Integrated super-heterodyne television receivers with multiple signal paths implemented using CMOS technology. An integrated circuit, includes: a plurality of CMOS (Complementary Metal-Oxide Semiconductor) low noise amplifiers; an adjustable frequency source; and one or more down-conversion mixers coupled with the adjustable frequency source and the plurality of CMOS low noise amplifiers to form a plurality of super-heterodyne receiving paths between an input to the plurality of CMOS low noise amplifiers and an output from one or more down-conversion mixers; where the integrated circuit is implemented on a single chip of semiconductive substrate.

Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

Abstract: Methods and apparatuses for blind equalizers with a hybrid adaptation error. In one embodiment, a Quadrature Amplitude Modulation (QAM) signal receiver, includes: a filter to reduce error in equalization, the filter to output a QAM signal; a decision engine coupled to the filter to determine a symbol based on the QAM signal; a first error generator coupled to the filter to compute a first error signal based on the QAM signal and a constant; a second error generator coupled to the filter and the decision engine to compute a second error signal based on the QAM signal and the determined symbol; an error combinator coupled to the first and second error generators to generate a combined error signal from the first and second error signals; and an adaptation engine coupled with the error combinator and the filter to reduce a equalization error according to the combined error signal.

Abstract: Processes and apparatuses for direct current (DC) offset cancellation using digital signal processing. Some embodiments of the invention are summarized in this section. In one embodiment, a circuit includes: an analog receiver; and a feedback circuit comprising a digital signal processor coupled with the analog receiver to generate a feedback signal to the analog receiver.

Abstract: Methods and apparatuses for blind equalizers with multiple constant modules. In one embodiment, a circuit, includes: a filter to produce an output based on an input that represents a symbol being received, the symbol being one of a Quadrature Amplitude Modulation (QAM) constellation; a decision engine coupled to the filter to generate a result indicating one region of a plurality of regions in a QAM constellation diagram, the output of the filter being in the indicated region which includes a plurality of symbols of different radii in the constellation diagram; and an error reduction engine coupled to the decision engine and the filter to reduce a difference between a selected one of a plurality of constants and a modulus of the output; where each of the plurality of constants correspond to one of the plurality of regions; and the selected one of the plurality of constants is selected according to the result of the decision engine.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.