Abstract: The present application relates to the technical field of computers. Provided are a method and apparatus for live migration of a virtual machine. The method comprises: when executing, in a virtual machine module on a destination host, an instruction of an instruction set that the destination host does not have but a source host has, trapping an exception; a system virtualization module intercepting the exception, and parsing an interrupt context of the exception; according to instruction address information of the interrupt context, acquiring data of the instruction, and decoding the same; and emulating an execution process of the instruction on the basis of the instruction set of the destination host. By means of the present application, the live migration of a virtual machine of cross-generation processors can be realized, while a higher instruction set capability is maintained.

Abstract: A duty cycle calibration circuit includes delay, temperature compensation, differential, and phase adjustment units. The delay adjustment unit receives a single-ended input clock signal to be calibrated and an adjustment voltage and outputs a single-ended clock signal adjusted by the adjustment voltage. The temperature compensation adjustment unit determines the adjustment voltage output by the temperature compensation adjustment unit, and provides the adjustment voltage to the delay adjustment unit to eliminate the influence of the temperature on the duty cycle. The differential adjustment unit converts the single-ended clock signal into a differential clock signal, and adjusts delay of the differential clock signal.

Abstract: A duty cycle calibration circuit and method solves duty cycle calibration without single ended I/O signals. The calibration circuit includes driving circuit and voltage divider units, a low-pass filter, voltage controlled oscillator, digital processing unit, and duty cycle adjustment unit.

Abstract: A delay device and a control method of transmission delay capable of performing temperature compensation are provided. The delay device includes a first current source, a second current source, a first resistor, and a delay adjustment circuit. The first current source is configured to provide a first current with a constant temperature coefficient. The second current source is connected to the first current source in parallel and is configured to provide a second current with a negative temperature coefficient. A first terminal of the first resistor is coupled to the first current source and the second current source. A second terminal of the first resistor is coupled to a reference ground terminal. The first resistor generates a control voltage at the first terminal of the first resistor according to the first current and the second current. The delay adjustment circuit is coupled to a transmission wire.

Abstract: A delay device and a delay control method are provided. The delay device includes at least one current-controlled delay group and at least one switch. The at least one current-controlled delay group is coupled to a transmission wire, each of the at least one current-controlled delay group includes at least one current-controlled delayer, and each of the at least one current-controlled delayer provides a delay according to a control voltage. The at least one switch is coupled between the at least one current-controlled delay group and the transmission wire, and each of the at least one switch is turned on or off according to a bit of an enable signal applied thereto. In the disclosure, the generated delay can be dynamically adjusted and cannot be affected by parasitic capacitance.

Abstract: The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

Abstract: A manufacturing method for a package substrate, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width. The second width is different from the first width, and the weaving direction of the fiberglass in the first dielectric layer is 90° relative to the weaving direction of the fiberglass in the second dielectric layer.

Abstract: The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

Abstract: The present disclosure provides an information tamper-resistant system and method. The system includes: a storage module; a writing module connected with the storage module through a first OTP switch, to write source information to the storage module; a first reading module connected with the storage module through a second OTP switch, to read out written information in the storage module and disconnect the first OTP switch and the second OTP switch after confirming that the written information is accurate; and a second reading module connected with the storage module through a third OTP switch, to read out information stored in the storage module after the third OTP switch is switched on; the first OTP switch, the second OTP switch, and the third OTP switch can only perform one switch-on operation or one switch-off operation. The system and method effectively avoid theft and tampering of information.

Abstract: The present disclosure provides an information tamper-resistant system and method. The system includes: a storage module; a writing module connected with the storage module through a first OTP switch, to write source information to the storage module; a first reading module connected with the storage module through a second OTP switch, to read out written information in the storage module and disconnect the first OTP switch and the second OTP switch after confirming that the written information is accurate; and a second reading module connected with the storage module through a third OTP switch, to read out information stored in the storage module after the third OTP switch is switched on; the first OTP switch, the second OTP switch, and the third OTP switch can only perform one switch-on operation or one switch-off operation. The system and method effectively avoid theft and tampering of information.

Abstract: A method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.

Abstract: A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.

Abstract: The application discloses a method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.

Abstract: A package substrate and a manufacturing method thereof, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width. The second width is different from the first width, and the weaving direction of the fiberglass in the first dielectric layer is 90° relative to the weaving direction of the fiberglass in the second dielectric layer.