Abstract: Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.

Abstract: Provided are a channel flatness compensation method, a channel flatness compensation apparatus, a storage medium, a baseband chip, and a device, wherein the method is applied to a transmitting link modulated by orthogonal frequency division multiplexing and includes: receiving an input vector of a current sub-carrier subjected to sub-carrier mapping processing, and determining current values of preset configuration parameters corresponding to the current sub-carrier; querying a preset frequency domain compensation table according to the current values of the preset configuration parameters, and determining a target compensation vector according to a query result; and determining an output vector of the current sub-carrier according to the input vector and the target compensation vector, wherein the output vector is used in an inverse fast Fourier transform operation.

Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

Abstract: Provided are a channel flatness compensation method, a channel flatness compensation apparatus, a storage medium, a baseband chip, and a device, wherein the method is applied to a transmitting link modulated by orthogonal frequency division multiplexing and includes: receiving an input vector of a current sub-carrier subjected to sub-carrier mapping processing, and determining current values of preset configuration parameters corresponding to the current sub-carrier; querying a preset frequency domain compensation table according to the current values of the preset configuration parameters, and determining a target compensation vector according to a query result; and determining an output vector of the current sub-carrier according to the input vector and the target compensation vector, wherein the output vector is used in an inverse fast Fourier transform operation.

Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.

Abstract: Provided are a reconfigurable processor and a reconfigurable processor system, where the reconfigurable processor includes: a hardware message management module (110), a memory management system (120) and an arithmetic and logic unit (130). The memory management system (120) is connected to the hardware message management module (110) and the arithmetic and logic unit (130) respectively; the hardware message management module (110) is configured to read and parse at least one hardware message, to configure a priority of each of the at least one hardware message and store each of the at least one hardware message into a memory through the memory management system (120); and the arithmetic and logic unit (130) is configured to run the at least one hardware message according to the configured priority.