Abstract: An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.

Abstract: A signal control circuit includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each signal line of the set of signal lines. A programmable synchronous three-state control circuit is connected to the set of three-state driver columns. The programmable synchronous three-state control circuit responds to a control signal and select signals to produce a three-state output enable signal which is applied to a selected three-state driver column of the set of three-state driver columns so as to control data signals on the data bus.

Abstract: A wireless communication system-on-a-chip comprises a system bus, a set of fixed function processors connected to the system bus, an embedded processor connected to the system bus, and reconfigurable logic connected to the system bus. The reconfigurable logic supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.

Abstract: A monolithic CMOS programmable digital intermediate frequency receiver includes a programmable memory, a clock generator, a sigma delta converter, a digital downconverter, and a decimation filter network. The programmable memory receives and stores a first value representative of a programmable parameter k and a second value representative of programmable parameter N. Coupled to the programmable memory, the clock generator generates a first clock signal, a second clock signal and a third clock signal. The first clock signal has a first frequency, fl, the second clock signal has a second frequency approximately equal to fl/k and the third clock signal has a third frequency approximately equal to fl/N. The sigma delta converter samples an analog input signal having an intermediate frequency using the first clock signal to generate a first set of digital signals. The digital downconverter mixes down the first set of digital signals using the second clock signal to generate a second set of digital signals.

Abstract: A configurable code generator system (CGS) for spread spectrum applications is disclosed herein. The CGS includes a composite code generator unit (CGU), a global code generator, and an interface that is coupled to the composite code generator and the global code generator. The CGU has multiple independent code generators, each capable of generating an independent code sequence. The global code generator provides a global code sequence for synchronization. The interface has memory that stores at least one bit of the global sequence and at least one bit from at least one of the independent code sequences of the CGU from which an output conditioning circuit can selectively choose based on a desired communication protocol.

Abstract: Information can be communicated to or from an electronic device in accordance with a plurality of protocols to provide a plurality of services for the user. The apparatus can operate with any conventional modulation (analog or digital) and in accordance with at least one of the plurality of protocols. If the user is a person, the services can include providing audio or tone signals. If the user is a device, the services can include providing audio, tone, or data signals. The electronic device is a receiver, a transmitter, or transceiver.

Abstract: A method of designing a circuit includes the step of establishing a matrix of circuit modules including sub-sets of circuit modules. A slice of circuit modules aligned along a first axis is selected from the matrix of circuit modules. The slice of circuit modules is replicated along a second axis to construct a logic structure with uniform height and width.

Abstract: A rake receiver in accordance with an exemplary embodiment of this invention is configurable by an external agent (e.g., microcontroller, DSP, or state machine) to suit the particular requirements of different spread spectrum systems. In an exemplary embodiment, the receiver includes multiple fingers. Each finger includes a plurality of generic despreaders/descramblers, a plurality of generic dechannelizers coupled to the despreaders/descramblers, and at least one timing estimation controller coupled to the despreaders/descramblers. The finger also includes at least one phase estimation controller, at least one frequency estimation controller, and at least one energy estimation controller all coupled to the generic dechannelizers.

Abstract: A programmable data arithmetic array includes a set of data buses and a matrix of data arithmetic units including fixed function units and programmable function units connected to the set of data buses. Bidirectional interconnect is positioned between the set of data buses and the matrix of data arithmetic units.

Abstract: A heterogeneous programmable gate array has an unstructured logic sub-array and a structured logic sub-array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic sub-array. A control signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver structured source signals therebetween.

Abstract: An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first signal line and the third signal line. Carry-in signal lines are attached to the first set of carry function generators. A second set of carry function generators are positioned between the second signal line and the fourth signal line. Intermediate carry signal lines are positioned between the first set of carry function generators and the second set of carry function generators. Carry out signal lines are attached to the second set of carry function generators. A first vertical carry chain comprises a first carry function generator from the first set of carry function generators and a first carry function generator from the second set of carry function generators.

Abstract: A programmable logic device includes an array of logic modules. A standard interconnection grid, with vertical routing lines, horizontal routing lines, and local routing lines, links the array of logic modules. An omniversal bus is positioned over the array of logic modules. The array of logic modules includes selective links to the omniversal bus, such that the omniversal bus dynamically establishes autonomous sub-arrays of logic modules of variable size attached to the omniversal bus.

Abstract: A method and apparatus for communicating information between a remote location and a user. Information from the remote location or the user is received by the inventive apparatus and processed by configurable circuitry to a form that can be received and used by the intended recipient. The reconfigurable circuitry can be changed manually by a human user or remotely through the receipt of appropriate signals. Accordingly, the apparatus can be reconfigured to be able to receive information that is transmitted in different forms from those forms that are receivable before reconfiguration.

Abstract: A method and apparatus for communicating information between a remote location and a user. Information from the remote location or the user is received by the inventive apparatus and processed by configurable circuitry to a form that can be received and used by the intended recipient. The reconfigurable circuitry can be changed manually by a human user or remotely through the receipt of appropriate signals. Accordingly, the apparatus can be reconfigured to be able to receive information that is transmitted in different forms from those forms that are receivable before reconfiguration.