Abstract: A method and arrangement for reducing power consumption in an M row×N column array of processing cells. A row mask register masks individual cells in each row for being enabled. A column mask register masks individual cells in each column for being enabled. The combination of the row mask register signal and column mask register signal enables or disables each cell of the array. Enabled cells are activated to execute an operation or function, while disabled cells a prevented from consuming dynamic power. Depending on the application and enabled cells thereby, power consumption is reduced.

Abstract: A hardware unit within a DSP includes various circuits and components that allow spreading, complex scrambling, and complex correlation to be performed at the software level in a programmable processor at the speed levels required by third generation wireless communication systems.

Abstract: A circuit employing an array of reconfigurable processing elements for wireless baseband processing. The circuit includes a first linear array of reconfigurable processing elements for processing signals from a first channel, and a second linear array of reconfigurable processing elements, coupled in parallel with the first linear array of reconfigurable processing elements, for processing signals from a second channel that is concurrent with the first channel. The circuit also includes a frame buffer array having a number of frame buffers that corresponds to a number of reconfigurable processing elements in the first and second linear arrays of processing elements. A point-to-point data bus is connected between each reconfigurable processor and an associated frame buffer. A shared data bus is connected between the first and second linear arrays of reconfigurable processing elements and the frame buffer array.

Abstract: Apparatuses and methods for decoding a bit stream of variable-length and fixed-length codewords representing encoded digital content. A decoder includes a memory for storing microinstructions that control the decoder. The decoder further includes a first barrel shifter for extracting a first bit field from the bit stream, a position of the first bit field being specified by the microinstruction, and a second barrel shifter for extracting a second bit field from the bit stream, a position of the second bit field being specified by the microinstructions. A microprogram counter keeps an address of a currently-executing microinstruction of the microinstructions, where a next state of the microprogram counter is determined by the microinstructions and the first bit field. A data converter modifies a value of the second bit field according to the microinstructions. A data storage stores either data in the microinstructions or an output of the data converter as decoded data values.

Abstract: A method and apparatus for convolution encoding and Viterbi decoding utilizes a flexible, digital signal processing architecture that comprises a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array. The core processor is operable to configure the re-configurable processing elements to perform data encoding and data decoding functions. A received data input is encoded by configuring one of the re-configurable processing elements to emulate a convolution encoding algorithm and applying the received data input to the convolution encoding algorithm. A received encoded data input is decoded by configuring the plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm wherein the plurality of re-configurable processing elements is configured to accommodate every data state of the convolution encoding algorithm.