Abstract: The present disclosure provides a method for estimating timing and/or frequency of a wireless signal; the method including the steps: receiving a digitally modulated signal; extracting a plurality of signal samples associated with a short training field (STF) of a PHY protocol data unit (PPDU) of an 802.11 frame; performing correlation operations on the plurality of signal samples to generate a predetermined number of correlation peaks; comparing the generated correlation peaks with a variable dynamic threshold; and calculating timing and/or frequency of the digitally modulated signal using the outcome of the comparing step.

Abstract: The present disclosure provides a method for estimating timing and/or frequency of a wireless signal; the method including the steps: receiving a digitally modulated signal; extracting a plurality of signal samples associated with a short training field (STF) of a PHY protocol data unit (PPDU) of an 802.11 frame; performing correlation operations on the plurality of signal samples to generate a predetermined number of correlation peaks; comparing the generated correlation peaks with a variable dynamic threshold; and calculating timing and/or frequency of the digitally modulated signal using the outcome of the comparing step.

Abstract: The present disclosure provides a method for estimating timing and/or frequency of a wireless signal; the method including the steps: receiving a digitally modulated signal; extracting a plurality of signal samples associated with a short training field (STF) of a PHY protocol data unit (PPDU) of an 802.11 frame; performing correlation operations on the plurality of signal samples to generate a predetermined number of correlation peaks; comparing the generated correlation peaks with a variable dynamic threshold; and calculating timing and/or frequency of the digitally modulated signal using the outcome of the comparing step.

Abstract: The disclosure is directed to a system and methods for waking-up a wireless receiver on a wireless network. The method includes the steps of: listening, by the wireless receiver, for signals in a predetermined frequency band periodically and decoding a wake-up key; validating the wake-up key by correlating the wake-up key with values stored in a memory using a first processing device; if the wake-up key is validated, decoding at least one PHY Protocol Data Unit (PPDU) and checking the value of one or more bits of the PPDU to validate the decoded PPDU as a wake-up PPDU; if the wake-up packet is validated, decoding a wake-up address and comparing the wake-up address to the station (STA) wake-up address; if the decoded wake-up address matches the STA wake-up address, powering-up a second processing device and confirming wake-up by exchanging an encrypted frame with Access Point (AP).

Abstract: The present disclosure provides a method for managing a sleep-mode of an electronic device that includes a processor, a memory and a communication interface configured to enable communication with a sleep-client device; the electronic device being arranged to enter the sleep-mode in predetermined circumstances to reduce power consumption; the method comprising the steps of: the electronic device modifying a value of a memory location associated with the communication interface; and the sleep-client device, reading a value of the memory location associated with the communication interface prior to transmitting data to the electronic device via the communication interface; wherein the memory location is representative of the availability of the electronic device to receive data via the communication interface.

Abstract: Systems and techniques are provided for performing wireless communications. In some aspects, an access point (AP) determines if buffered data traffic is available that will be advertised to one or more wireless communication devices using a beacon frame scheduled for broadcast by the AP. The AP broadcasts a pre-determined frame in response to determining buffered data traffic is not available, and the AP may skip broadcasting an upcoming beacon frame associated with the pre-determined frame. For example, the AP broadcasts the upcoming beacon after broadcasting the pre-determined frame when there is a change of configuration or when a resynchronization interval associated with the one or more wireless communication devices has been exceeded.

Abstract: Systems and techniques are provided for performing wireless communications. In some aspects, an access point (AP) determines if buffered data traffic is available that will be advertised to one or more wireless communication devices using a beacon frame scheduled for broadcast by the AP. The AP broadcasts a pre-determined frame in response to determining buffered data traffic is not available before broadcasting the beacon frame. A wireless communication device exits a low-power mode to receive an upcoming beacon frame or receive a pre-determined frame broadcast by the AP. Based on receiving the pre-determined frame, the wireless communication device determines that the upcoming beacon frame does not advertise buffered data traffic addressed to the wireless communication device and returns to the low-power mode after decoding at least a portion of the pre-determined frame.

Abstract: The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.

Abstract: The present disclosure provides an electronic circuit having one reference current terminal arranged to connect to a reference current generator, an MOS current mirror stage, an MOS push-pull amplifier stage operatively coupled to the current mirror stage and the current mode amplifier stage.

Abstract: A subchannel detection system for a wireless communication device is disclosed. The system includes an input interface arranged to receive digital data over a predetermined baseband having a plurality of subchannels a plurality of frequency translators arranged to shift the spectrum of the digital data within a subchannel to the center of the baseband, a plurality of low-pass filters arranged to filter frequencies in the middle of the baseband within a subchannel bandwidth, a plurality of correlators arranged to receive a filtered digital signal and correlate the received signal to a subchannel size, and a processing module arranged to receive data from the plurality of correlators and detect one or more active subchannels. The plurality of frequency translators shift the spectrum of all subchannels in the digital data to the center of the baseband; the shifted spectra are filtered by the plurality of low-pass filters and correlated to individual subchannels.

Abstract: The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.

Abstract: The present disclosure provides a method for estimating timing and/or frequency of a wireless signal; the method including the steps: receiving a digitally modulated signal; extracting a plurality of signal samples associated with a short training field (STF) of a PHY protocol data unit (PPDU) of an 802.11 frame; performing correlation operations on the plurality of signal samples to generate a predetermined number of correlation peaks; comparing the generated correlation peaks with a variable dynamic threshold; and calculating timing and/or frequency of the digitally modulated signal using the outcome of the comparing step.

Abstract: The present disclosure provides a method for managing a sleep-mode of an electronic device that includes a processor, a memory and a communication interface configured to enable communication with a sleep-client device; the electronic device being arranged to enter the sleep-mode in predetermined circumstances to reduce power consumption; the method comprising the steps of: the electronic device modifying a value of a memory location associated with the communication interface; and the sleep-client device, reading a value of the memory location associated with the communication interface prior to transmitting data to the electronic device via the communication interface; wherein the memory location is representative of the availability of the electronic device to receive data via the communication interface.

Abstract: An electronic circuit for voltage regulation is disclosed, the circuit generally includes a low-dropout (LDO) voltage regulator function block, including a primary feedback loop, and an output voltage stabilizer block connected to the LDO voltage regulator function block outside the primary feedback loop, wherein the output voltage stabilizer block includes a plurality of peak voltage suppression circuits and a plurality of dip voltage suppression circuits. In some embodiments, the output voltage stabilizer block is set at low bias current to minimize current consumption at normal condition. Other useful features and advantages of an electronic circuit for voltage regulation are disclosed.

Abstract: The disclosure is directed to a system and methods for waking-up a wireless receiver on a wireless network. The method includes the steps of: listening, by the wireless receiver, for signals in a predetermined frequency band periodically and decoding a wake-up key; validating the wake-up key by correlating the wake-up key with values stored in a memory using a first processing device; if the wake-up key is validated, decoding at least one PHY Protocol Data Unit (PPDU) and checking the value of one or more bits of the PPDU to validate the decoded PPDU as a wake-up PPDU; if the wake-up packet is validated, decoding a wake-up address and comparing the wake-up address to the station (STA) wake-up address; if the decoded wake-up address matches the STA wake-up address, powering-up a second processing device and confirming wake-up by exchanging an encrypted frame with Access Point (AP).

Abstract: A subchannel detection system for a wireless communication device is disclosed. The system includes an input interface arranged to receive digital data over a predetermined baseband having a plurality of subchannels a plurality of frequency translators arranged to shift the spectrum of the digital data within a subchannel to the center of the baseband, a plurality of low-pass filters arranged to filter frequencies in the middle of the baseband within a subchannel bandwidth, a plurality of correlators arranged to receive a filtered digital signal and correlate the received signal to a subchannel size, and a processing module arranged to receive data from the plurality of correlators and detect one or more active subchannels. The plurality of frequency translators shift the spectrum of all subchannels in the digital data to the center of the baseband; the shifted spectra are filtered by the plurality of low-pass filters and correlated to individual subchannels.

Abstract: An electronic circuit for voltage regulation is disclosed, the circuit generally includes a low-dropout (LDO) voltage regulator function block, including a primary feedback loop, and an output voltage stabilizer block connected to the LDO voltage regulator function block outside the primary feedback loop, wherein the output voltage stabilizer block includes a plurality of peak voltage suppression circuits and a plurality of dip voltage suppression circuits. In some embodiments, the output voltage stabilizer block is set at low bias current to minimize current consumption at normal condition. Other useful features and advantages of an electronic circuit for voltage regulation are disclosed.

Abstract: A radio frequency transmitter including two digital to analog converter circuits. The two radio frequency digital to analog converter circuits are configured to operate independently or operating in unison. Operating independently includes each radio frequency digital to analog converter circuit of the two radio frequency digital to analog converter circuits receiving separate baseband signals and separate local oscillation inputs. Operating in unison includes both of the two radio frequency digital to analog converter circuits receiving a single baseband signal and a single local oscillation input. The two radio frequency digital to analog converter circuits are configured to change between operating independently and operating in unison.

Abstract: Various circuitry may benefit from appropriate matching. For example, certain low noise broadband amplifiers may benefit from resistive matching.