Abstract: The invention relates to a method for the preparation of porous polymeric fibres comprising functionalized or active particles. By extruding a mixture of one or more dissolved polymers with particulate material a porous fibre is obtained in which the particulate material is entrapped. Extrusion of the fibre occurs under two-step phase inversion conditions. In particular the porous fibres can be used for the isolation of macromolecules such as peptides, proteins, nucleic acids or other organic compounds from complex reaction mixtures, in particular from fermentation broths. Another application is the immobilization of a catalyst in a reaction mixture.

Abstract: The invention relates to a hollow or solid fibre having multiple porous layers concentrically arranged, and wherein at least one of the layers comprises functionalized or active particles that are well accessible and maintain their function after preparation. The layer containing high loads of particles can be either the outer or the inner layer. The main function of the other porous layer is to provide mechanical stability to the fibre. It can further act as a sieve and prevent unwanted compounds or species to come in contact with the functionalized particulate matter. Where it is the inner layer, the second layer can advantageously be a biocompatible material. With the second being the outer layer it is now possible to reach a particle content of 100 wt % in the inner layer.

Abstract: A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.

Abstract: The invention relates to a method for the preparation of porous polymeric fibres comprising functionalized or active particles. By extruding a mixture of one or more dissolved polymers with particulate material a porous fibre is obtained in which the particulate material is entrapped. Extrusion of the fibre occurs under two-step phase inversion conditions. In particular the porous fibres can be used for the isolation of macromolecules such as peptides, proteins, nucleic acids or other organic compounds from complex reaction mixtures, in particular from fermentation broths. Another application is the immobilization of a catalyst in a reaction mixture.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.

Abstract: Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding sites on the surface of the wafer 10, 201 to which chips 11 are bonded to form a hybrid monolithic wafer system. The wafer 10 is packaged within a wafer package, FIG. 4, and the packaging system utilizes a header 20 which is a flexible circuit connector between the wafer package and first level circuit board 30.

Abstract: Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer 21 is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding.

Abstract: A computer and switching mainframe connection system and flat cable connection elements therefor. The elements are a flat cable "S" circuit, FIG. 1, and a bus circuit, FIG. 8. The "S" circuit has an elongated run (68) and a "S" portion (43). The bus circuit has "U" elements (61) and a linear portion (58) with the signal lines of the "U" elements (61) connected to the signal lines of the bus circuit (80). The mainframe is formed of an array of circuit boards (100) bearing a wafer (90) and header (99) for the wafer which in turn is connected to ports (101) to which tab connectors (57, 56, FIG. 3) of the bus circuit and "S" circuit are connected.

Abstract: Disclosed is a wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively.The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.