Abstract: Apparatus and a method for latching a column address in a DRAM, having increased speed and no race conditions. The method is comprised of the steps of receiving column select and column address input signals, enabling detection and indication, by generation of an indication signal, of the presence of each stable column address input signal upon the presence of a column select signal, summing the indication signals, and operating a latch by each of the column address input signals whereby a DRAM column can be addressed upon enabling by the summed indication signals, whereby the latching is not enabled without a first indication of the presence of a stable column address and whereby the first indication is prevented without the earlier presence of a column select signal.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A method and apparatus for precharging memory cell bit storage capacitors and bit lines of a DRAM from a single source. The storage capacitor reference plate is driven from a high impedance voltage divider, minimizing the effects of voltage supply noise, so that noise does not couple into the storage capacitor and turn on the associated capacitor access transistor. At the same time the bit line is driven from a low impedance drive, to enable it to maintain the bit line midpoint voltage. The bit line precharge voltage is referenced to the storage capacitor reference voltage providing good cell margin.

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.

Abstract: An address transition detection circuit which uses fast inverters in a delay line, avoiding filtering of input pulses and providing significant threshold voltage margin for the input address signal. A pair of gates connected to various points of the delay line detect at at least one point the presence of an address transition passing along the delay line.

Abstract: A digital to analog converter comprising a differential amplifier formed of a pair of similar conductivity type field effect transistors, one transistor being connected to a load for driving the load in synchronism with a digital input signal, means for applying a reference voltage to the gate of the second transistor, and a third field effect transistor of conductivity type complementary to said one transistor, connected with its source-drain circuit in series with the source-drain circuit of the second transistor to a second reference voltage, and means for driving the gates of said one and third transistors together with said digital input signal, whereby the first and third transistors are synchronously and oppositely driven to conduct and cut off, thus ensuring substantially no current flow in the second transistor while the first transistor is conducting.

Abstract: A bandgap voltage generator useful in CMOS integrated circuits using intrinsic bipolar transistors. The generator is comprised of a pair of bipolar voltage generator which utilizes bipolar devices in a common collector configuration. Therefore for the first time a bandgap voltage reference using the intrinsic vertical bipolar transistor can be implemented in a CMOS chip without the need for an operational amplifier.

Abstract: A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.

Abstract: A dynamic random access memory having a serial access data port. A plurality of complimentary bitline pairs are provided for receiving data signals from a plurality of memory cells, and a plurality of latches are connected to respective ones of the bitline pairs for periodically sensing and restoring the data signals in the memory cells. Predetermined ones of the latches are connected together via a plurality of isolation transfer gates which are enabled according to a predetermined timing sequence for unidirectionally shifting the data signals therebetween according to a master-slave action.

Abstract: A DRAM semiconductor memory chip comprised of a matrix of rows and columns having a bit storage cell at each location, means for receiving row and column address bits in multiplexed form on a single address bus, the multiplexing arrangement being such that the number of column address bits exceeds the number of row address bits, whereby a system using the DRAM memory chip has access to an enlarged page size.

Abstract: A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.

Abstract: An inexpensive edge programmable timing signal generator for generating timing signals having complete edge programmability for accommodating incrementally adjustable variable pulse widths. The timing circuit is particularly useful in memory testing devices, where generation of a multiplicity of clock phases is required. A delay register delays an input timing signal generated by a coarse timing circuit by a predetermined amount of time, and a pair of rising and falling edge delay lines receive and delay the input and delayed timing signals by further predetermined amounts of time. The signals output from the rising and falling edge delay lines are applied to an OR gate, the output of which is applied to an EXCLUSIVE OR gate for selectively inverting the signal output from the OR gate. The circuit is inexpensive and takes up very little circuit board area.