Abstract: A latch ram including on a single chip a memory array, a multiplexed address and data bus for the input of address information and the input/output of data information on the same lines, an address latch and associated row and column decoders for addressing particular locations within the memory array, data I/O and associated column I/O circuitry for inputting data to and outputting data from the memory array, and microprocessor-controlled logic for controlling the input and output of such data. The device is packaged in a 28-pin SOG or TSOP package.