Abstract: An n-stage charge pump contains n primary capacitive elements (CC1-CCn or CD1-CDn), n+1 charge-transfer cells (601-60n+1, 1101-110n+1, 1201-120n+1, or 1301-130n+1) respectively sequentially designated as the first through (n+1)th cells, and sources of first and second clock signals (VCKP and VCK P or VCKP1 and VCKP2) approximately inverse to each other. Each pump stage (62i, 112i, 122i, or 132i) includes one (CCi or CDi) of the capacitive elements and a corresponding one (60i, 110i, 120i, or 130i) of the first through nth charge-transfer cells. Each cell contains a charge-transfer FET (PTi or NTi). A pair of side FETs (PSi and PDi or NSi and NDi) are provided in the first cell, in the (n+1)th cell, and normally in each remaining cell. The side FETs in the first cell or/and the (n+1) cell are connected in such a manner as to avoid undesired bipolar action that could cause degradation in the pump's voltage gain.

Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

Abstract: The present invention provides a method and system for providing timing adjustments to perform reliable optical recording at high speeds. The present invention includes performing a timing adjustment in a coarse increment to a write control signal using a clock with a cycle less than T, where T is a fundamental unit of time for a data mark; and performing a timing adjustment in a fine increment to the write control signal using a time delay technique. The method and system in accordance with the present invention provides a write control logic which allows for multiple levels of time adjustment for each type of mark. In the preferred embodiment, a dual level timing adjustment technique is provided. The first level provides coarse timing adjustments using a clock with a cycle less than T and parameters to control the power level and time duration of each mark. The second level provides fine timing adjustments using time delay techniques.

Abstract: The present invention provides a method and system for window realignment to correct the data frame boundaries of data from an optical media. The present invention includes: determining if a sync pattern for a data frame is within a sync window; opening an extended sync window, if the sync pattern for the data frame is not within the sync window; determining if the sync pattern for the data frame is within the extended sync window; and realigning the sync window to the sync pattern in the extended sync window, if the sync pattern is within the extended sync window. The present invention utilizes an extended sync window to realign the sync window when the number of missing sync patterns in a data stream has exceeded a threshold number. In the preferred embodiment, the width of the extended sync window and the threshold number are programmable. In this manner, the sync window can be realigned before shifting of the data renders the data uncorrectable.

Abstract: The present invention provides a method and system for providing a header search in a data read from an optical medium. The method includes opening a search window with a size greater than one sector; finding at least one valid header within the search window; and locating a target sector based upon the at least one valid header. The size of the window is programmable. Optionally, more than one valid header can be required to be found before they are used as the reference, for the purpose of increasing the reliability of the reference. The number of required valid headers is also programmable. Buffering of the data then begins at the target sector found based on the reference. The header of this target sector is then checked for validity. If the header is not the target, then the header search may be restarted without the need to redo the data read. The header search scheme is applicable for multiple optical data formats.

Abstract: The present invention provides an integrated controller to process both optical reads and optical writes of multiple optical media. The integrated controller includes a host interface; a buffer manager coupled to the host interface; an embedded memory coupled to the buffer manager; an integrated encoding/decoding engine coupled to the buffer manager; a data channel interface coupled to the integrated encoding/decoding engine; and an integrated servo/recording processor coupled to the integrated encoding/decoding engine and the data channel interface, where the integrated servo/recording processor includes a set of write strategies. The present invention provides a controller which integrates the functionality of the conventional controllers into an integrated processor. With the controller in accordance with the present invention, a single drive may be provided which can read CD-based and DVD-based formats, read and write to Write Once Media, and read and write to Rewritable Media.

Abstract: The present invention provides a method and system for servo control in an optical drive. The method includes initiating an execution of a multiplier and accumulator controller (MAC) by a processor; and automatically calculating a transfer function by the MAC based upon a sample servo data. The present invention provides a servo control system which utilizes a MAC which is directly linked to the sample servo data. When a processor commands the MAC to execute, the MAC receives the sample servo directly from an Analog-to-Digital Converter (ADC); retrieves the corresponding accumulated sample servo data from a memory; calculates the transfer function; and stores the results back into the memory. The processor then accesses the memory to retrieve the result. Because the MAC is able to calculate the transfer function with minimal intervention from the processor, significant processing resources and time are saved.

Abstract: The present invention provides a method and system for syndrome generation for data from an optical media. The method includes reading data bytes for a plurality of columns of a row of the data; reading a plurality of partial syndromes from a memory, each of the plurality of partial syndromes corresponding to one of the plurality of columns; updating each of the plurality of partial syndromes with the data byte of the corresponding column; and writing the plurality of updated partial syndromes into the memory. The present invention obtains data bytes for multiple columns at one time. Syndrome generation is then performed for each column, with the partial syndromes for each column stored in a memory. As the data bytes of subsequent rows of data for multiple columns are obtained, the partial syndromes for each column are read from the memory and loaded into a syndrome generation logic, thus updating the partial syndrome for each column. The updated syndromes are written back into the memory.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

Abstract: In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

Abstract: In a semiconductor dynamic random access memory, a single path data pipeline for applying voltages from a sense amplifier to a data output pad for different column address signal (CAS) latencies comprising: a dual input single output latch, the dual inputs coupled to data bit (S1) and data bit bar (S1) outputs of a sense amplifier and producing a single bit data output in response thereto, a buffer circuit coupled to the output latch and operable in response to enable signals (EN, EN) for passing the data output from the latch, a dual input multiplexer (mux) with each input having a circuit for receiving the data output from the buffer circuit, one input circuit including a delay circuit for delaying application of the data output from the buffer circuit to the mux, the mux operable in response to a column address (CAS) latency signal to pass one of two signals, and logic gates coupled to pass the mux output to control the application of a voltage to a data output pad.

Abstract: A decoder for use in addressing a spare column select line for use in a semiconductor random access memory includes a plurality of input lines each connected to a Y predecoder line, each input line including a pass gate for passing the bit connected thereto in response to an enable signal and a fuse link serially connected with a pass gate, a plurality of fuse links being connected in parallel to provide one of a first plurality of address inputs, a logic gate for receiving said first plurality of address inputs from said plurality of input lines and generating a spare column select signal, whereby all decoder pass gates are disabled until the spare word line is selected for use, the address for the spare line being defined by ablation of fuse links in unwanted Y predecoder lines.

Abstract: A semiconductor device disables itself during power-up until the internal power supply voltage and other circuits reach states in which the device can operate properly. The internal power supply voltage is coupled to the input terminal of an inverter through a delay network. During power-up, the device remains disabled until the voltage at the input terminal of the inverter reaches the inverter trip point. The delay network and the inverter are designed so that the voltage at the inverter's input terminal does not reach the inverter trip point until the internal power supply voltage and other circuits have reached states in which the device can operate properly. When the (device is turned off, the inverter input terminal is discharged quickly by a diode or resistor. Therefore, if the power is turned back on immediately, a suitable delay will be provided.

Abstract: A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude.

Abstract: A fuse-programmable circuit controllably enables or disables an electrical signal (S). The circuit includes a transmission gate (118) connected between the circuit's input and output terminals. The transmission gate is controlled by complimentary outputs OUTH, OUTL of a fuse-programmable latch (130). A PMOS transistor (Q41) and a fuse (F41) are connected in series between the output terminal and a power supply voltage (VCC). An NMOS transistor (Q42) and a fuse (F42) are connected in series between the output terminal and a reference voltage (ground). The gate of the PMOS transistor is connected to the latch output OUTH. The gate of the NMOS transistor is connected to the latch output OUTL. When OUTH is high and OUTL is low, the transmission gate couples the signal (S) from the input terminal to the output terminal. When OUTH is low and OUTL is high, the transmission gate is closed.

Abstract: A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

Abstract: A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

Abstract: The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

Abstract: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off.