Abstract: A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

Abstract: A frequency measurement circuit includes a counter circuit to receive a first digitally-controlled oscillator (DCO) clock signal corresponding to a first DCO input codeword and a measurement signal. The counter circuit is responsive to the measurement signal to generate a count representing a measured frequency of the first DCO clock signal. A control circuit is configured to selectively adjust a parameter of the measurement signal for generating a second count of a second DCO clock signal corresponding to a second DCO codeword. The control circuit selectively adjusts the parameter based on a received control signal.

Abstract: A delay circuit includes a delay line including at least a first group of delay elements. The delay line is responsive to a first digital delay code to delay an input signal by a first delay value, and responsive to a change from the first digital delay code to a second digital delay code to delay the input signal by a second delay value. Control circuitry generates the first and second digital delay codes. Glitch monitoring circuitry couples to the control circuitry to conditionally gate the change from the first digital delay code to the second digital delay code based on a prediction of a glitch condition.

Abstract: A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO) coupled to the output of the loop filter. The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The method includes determining a calibration DCO codeword representing a calibration operating point for the locked-loop circuit; determining a scaling factor based on the calibration operating point, the scaling factor based on a ratio of an actual DCO gain to a nominal DCO gain; and applying the scaling factor to operating parameters of the loop filter.

Abstract: A method of operation in a locked-loop circuit. The locked-loop circuit includes a loop filter and a digitally-controlled oscillator (DCO). The loop filter includes a first input to receive a digital word representing a difference between a reference clock frequency and a DCO output frequency. The loop filter includes internal storage. The method includes selecting a desired DCO output frequency that is generated in response to a calibration DCO codeword. A start value is retrieved from the loop filter internal storage. The start value corresponds to the calibration DCO codeword. The locked-loop circuit is then started with the retrieved start value.

Abstract: An integrated circuit (IC) includes multiple interconnected driver cells enabled/disabled based on a first set of control signals. The multiple circuit cells are arranged to define a first aggregate enabled/disabled configuration exhibiting a first aggregated delay. The first aggregated delay is based on the individual enabled/disabled states of the circuit cells. Timing circuitry evaluates the first aggregate delay with respect to a circuit design constraint, and selectively generates a second set of control signals to configure the multiple circuit cells to define a second aggregate enabled/disabled configuration having a second aggregate delay different than the first aggregate delay.

Abstract: A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.

Abstract: A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.

Abstract: An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.

Abstract: A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.

Abstract: An integrated circuit (IC) device is disclosed. The IC device includes a global clock source to generate a global clock signal. Multiple local clock sources are employed in the IC device. Each local clock source provides a local clock signal for a partitioned sub-design block in the IC device. Each local clock signal is based on the global clock signal. The IC device includes a clock controller having inputs from the global clock source and the multiple local clock sources. The clock controller (1) measures skew between each local clock source and the global clock source, and (2) generates respective control signals to adjust respective phases of each local clock signal to reduce the measured skew.

Abstract: A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.

Abstract: A locked-loop circuit includes a time-to-digital converter (TDC) having a reference clock input and an error input. A digital loop filter receives an output from the TDC representing a difference between the reference clock input and the error input. A digitally-controlled oscillator (DCO) receives an output from the digital filter in the form of output bits. The DCO has a codeword gain associated with a DCO control word. The codeword gain is applied to the output bits received from the digital loop filter. Calibration logic determines a scaling factor based on a process-voltage-temperature (PVT) operating characteristic. The scaling factor is applied to normalize an actual DCO codeword gain to the codeword gain. The DCO includes an output to deliver an output timing signal having a frequency based on the scaling factor.

Abstract: A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.

Abstract: A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.

Abstract: A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.

Abstract: A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.

Abstract: A reconfigurable phase-locked loop integrated circuit is disclosed which is coupleable to an inductor, and may include: a memory storing a plurality of configuration parameters; a plurality of capacitive tuning circuits coupleable to the inductor to form an LC oscillator circuit to generate a first output signal having a first output frequency; a reconfigurable frequency and delay generator configurable as a ring oscillator or as a delay line circuit, and to generate a second output signal having a second output frequency; and a first digital controller to generate a first control signals to the reconfigurable frequency and delay generator to generate the second output signal having the second output frequency when the reconfigurable frequency and delay generator is configured as the ring oscillator; and to generate a second plurality of control signals to the plurality of capacitive tuning circuits to generate the first output signal having the first output frequency when the reconfigurable frequency and del

Abstract: A digital control loop circuit is disclosed which is coupleable to an oscillator to form a configurable, digital phase-locked loop to generate an output signal having a configurable or selectable output frequency. A representative embodiment of the digital control loop circuit may include a memory storing a plurality of configuration parameters, at least one configuration parameter specifying the output frequency; and a digital controller coupleable to receive an input signal from a reference frequency generator having a reference frequency, the digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the oscillator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.