Patents Assigned to Mplicity Ltd.
  • Chip area optimization for multithreaded designs
    Patent number: 7500210
    Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: March 3, 2009
    Assignee: Mplicity Ltd.
    Inventors: Gil Vinitzky, Eran Dagan
  • Chip area optimization for multithreaded designs
    Publication number: 20080115100
    Abstract: A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 15, 2008
    Applicant: MPLICITY LTD.
    Inventors: Gil Vinitzky, Eran Dagan