Abstract: A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

Abstract: A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.