Abstract: The current invention provides simplifications to the user equipment (UE) radio front end module for the cellular handset or dongle through modification of the existing 3GPP specifications for LTE and WCDMA/HSPA+ in order to support half duplex (HD) operation. The option to support HD operation is provided without mandating upgrades to all existing base stations that have already been deployed. The instant invention further prevents HD UEs from attaching to any base stations which do not support HD operations. The instant invention further provides inter-frequency cell search periods for enabling HD UEs to communicate with any base stations/cells supporting the HD operations. The instant invention further enables the HSPA+ system to support the HD-FDD mode.

Abstract: The invention describes a method for predicting the performance of the MLD receiver in MIMO channels. The method is based on the iterative principle where the performance of the MLD decoder is derived from that of an iterative receiver architecture with similar performance. The described Iterative MIMO Effective SNR (IMES) technique maps the performance of each MIMO channel realization into a set of effective SNR values for the different streams. This set of effective SNR values can then be used to provide link adaptation feedback to the transmitter so that the most suitable transmission format can be selected according to the characteristics of the propagation channel. Alternatively, this information can be used to adapt the receiver processing to the channel conditions, thereby making it possible, for example, to reduce the receiver power consumption in good signal conditions.

Abstract: The present invention discloses a continuous voltage controlled oscillator (VCO) frequency temperature compensation apparatus for a phase locked loop (PLL) and a continuous VCO frequency temperature compensation method for a PLL. The system utilizes a VCO with one digital coarse tuning input, a first analog fine tuning input, and a second analog fine tuning input. The system uses the second analog fine tuning inputs to compensate the VCO for frequency shifts due to temperature fluctuation. When the PLL transitions to the fine lock (FL) mode, the system starts driving the second fine tuning input with a differential amplifier. The differential amplifier compares the first fine tuning input with a reference voltage, and drives the second fine tuning input to compensate the first fine tuning input.

Abstract: The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.