Abstract: A method for arbitrating for control of a network medium for transmission, combining aspects of the time slots and collision-based arbitration schemes by dynamically modifying the scheme used in accordance with network load. In a preferred embodiment, this is done by assigning time slots to the various nodes and arbitrating using the time slots when the network is free. If there are no requests for use of the network after a predefined number of time slots, any node can immediately access the network using a collision-detection method without being required to wait for a time slot arbitration procedure.
Abstract: An oscillometric method for determining hemodynamic parameters of the arterial portion of patient's circulatory system, consisting in recording the pulse pressure waves in the major arterial vessel under examination, under the effect of a linearly varying pressure in a pneumatic vessel-constricting pressure cuff, with the result that a closed contour is formed within a single measuring cycle, which is established by straight lines the points of intersection of which are the signs of arterial pressure, while the amplitude values of the pulse waves in the contour determine the geometric parameters of the major arterial vessel under examination. A measuring system for carrying the method into effect features a linear characteristic of conversion and a straight horizontal amplitude-frequency characteristic in a frequency range of approximately from 0 to 50 Hz along a through path of conversion, amplification, and recording.
Type:
Grant
Filed:
November 8, 1994
Date of Patent:
November 18, 1997
Assignee:
MTI, Ltd.
Inventors:
Viacheslav Nikolaievich Ragozin, Vladimir Alexandrevitch Degtiarev
Abstract: An improvement on the use of parity and a write cache for a RAID by adding a check code for the parity data itself. In addition, the time during which the parity check code is unprotected is reduced by using a single loop to calculate the old parity check code and verify it, determine the new parity information itself from the new write data, and calculate the new parity check code. Rather than cycle through all the parity blocks to calculate the old check code, and verify that it matches what is stored, the old check code is reconstructed block-by-block as the new parity is generated for each block in a loop. In addition, the new parity check code is constructed bit-by-bit at the same time.
Abstract: A wireless caller identification system employing master and remote units. Microcontrollers at both master and remote units facilitate secure communications between units, providing the identity of the source of calls received at the master unit over a connected telephone line from a telephone central office. Radio frequency (RF) or infrared (IR) modes of communication may be used.
Abstract: A method and apparatus by which the partial error check value for all preceding data in a sector is updated each time a new data item is written into a data buffer during a transfer from a host computer to a system storage device. The partial check value is written into the buffer location following the location containing the most recently buffered data item from the associated sector. Thus, after the entire sector has been transferred into the buffer, the final check value for that sector will be available in the buffer location following the location containing the last written data from the associated sector. Upon readback of a sector from the storage device, the sector size is longer by one data item since the appended check value is treated as the last data item of the sector. When the sector is read back from the storage device, the check value is again updated with the entry of each data item.
Abstract: Method and apparatus for the reduction of the intensity of magnetic field emissions from display devices and other magnetic field emitters comprising an active magnetic field bucking system and a passive magnetic shield, for use either singularly or in combination. Various circuits are disclosed for generating a bucking current necessary to buck the emitted magnetic field. The magnetic shield comprises a material selected from the group consisting of manganese or aluminum doped yttrium aluminum or yttrium iron garnet, iron doped glass, iron based thin films, ferrous fluoride, ferrous borate, and combinations thereof.
Abstract: A dental handpiece having a slow speed, high torque rotary output, comprises a housing member; an input shaft rotatably mounted in the housing member; a coupling member at an end portion of the input shaft for being coupled to a rotary dental drive unit; a plurality of planetary gear stages sequentially arranged within the housing member, a first of the planetary gear stages being coupled so as to be rotationally driven by the input shaft; subsequent planetary gear stages being sequentially coupled to each other such that an output of one planetary gear stage drives an input of a next subsequent planetary gear stage; and an output shaft coupled to a final output planetary gear stage of the plurality of sequentially arranged planetary gear stages. The output shaft provides a slow speed, high torque rotary output responsive to the input shaft being driven by a higher speed rotary dental drive unit.
Abstract: Method and apparatus for the reduction of the intensity of magnetic field emissions from video display units (VDU) in the vicinity of the user comprising a wire coil shaped to mimic the shape of conventional VDU deflection coils draped over a VDU to produce a cancelling magnetic field synchronous with the magnetic field produced by the unit's deflection coil. The cancellation coil is driven by a signature sensor disposed forward of the deflection coil that senses the characteristics of the magnetic field produced by the deflection coil. The gain of the cancellation coil is adjusted to maximize the cancellation coil's cancellation effect in the vicinity of the VDU user.
Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.
Type:
Grant
Filed:
April 7, 1994
Date of Patent:
January 16, 1996
Assignee:
MTI Technology Corporation
Inventors:
David H. Jaffe, Hoke S. Johnson, III, Chris W. Eidler
Abstract: A method and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. More particularly, there is provided a method and apparatus for determining, on restoration of power to a device set, whether or not a write operation was interrupted when power was removed, and for reconstructing any data that may be inconsistent because of the removal of power.
Type:
Grant
Filed:
April 6, 1994
Date of Patent:
December 12, 1995
Assignee:
MTI Technology Corporation
Inventors:
Randy H. Katz, David T. Powers, David H. Jaffe, Joseph Glider, Thomas E. Idleman
Abstract: An inverter circuit operating from line utilizes minimum, lower rating switches to operate at higher frequency, while maintaining substantially unity power factor and lower input current harmonics. The input rectified DC is transferred to a storage capacitor using a buck-boost regulator in which the current in inductor is always maintained discontinuous and proportional to the instantaneous input voltage. Filtering this input current will give substantially sinusoidal current at the input. The second switch in the buck-boost regulator and an additional third switch contributes to the necessary half bridge for an inverter. The inverter, which can be self oscillating or driven from a control circuitry, can give higher frequency, high voltage AC output with ability to control the load power hence provide for dimming, e.g. for a fluorescent lamp.
Abstract: A lighting system comprising: an AC power line; an electronic ballast including structure for receiving and interpreting commands transmitted on the power line to control dimming of a fluorescent lamp, the ballast including structure defining an individual address, the ballast including structure for initiating an arc to start the fluorescent lamp, for limiting current through the fluorescent lamp after the arc is initiated, and for dimming the light output of the fluorescent lamp; and a control element spaced apart from the electronic ballast and including structure for sending commands on the power line in a format that the ballast is capable of interpreting, the control element including structure for sending an address with the command, the ballast including structure for comparing the sent address with its individual address and responding to the command if the sent address matches its individual address.
Abstract: Methods and apparatus are provided for detecting and correcting various data errors that may arise in a mass data storage apparatus comprising a set of physical mass storage devices operating as one or more larger logical mass storage devices. A method and apparatus is provided for detecting and reconstructing incorrectly routed data. A method and apparatus is also provided for detecting when one or more physical devices fails to write a block of data, and for reconstructing lost data.
Type:
Grant
Filed:
February 21, 1995
Date of Patent:
November 21, 1995
Assignee:
MTI Technology Corporation
Inventors:
Joseph S. Glider, David T. Powers, Thomas E. Idleman
Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.
Type:
Grant
Filed:
February 24, 1995
Date of Patent:
September 26, 1995
Assignee:
MTI Technology Corporation
Inventors:
Kumar Gajjar, Kaushik S. Shah, Duc H. Trang
Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.
Type:
Grant
Filed:
April 6, 1990
Date of Patent:
May 9, 1995
Assignee:
MTI Technology Corporation
Inventors:
Larry P. Henson, Kumar Gajjar, Thomas E. Idleman
Abstract: A network-type data processing system is provided. The system can support multiple simultaneous exchanges of data, and includes multi-port storage devices in which all ports can be active at all times. On initialization of the system, each storage device can announce itself through all of its ports simultaneously.
Abstract: A data storage system having a local processor and a plurality of memory storage elements is used for storing data from one or more external CPUs. The storage system includes a plurality of memory buffers, each coupled to a separate memory storage element. A data path control circuit is programmed by the local processor to control the transfer of data between the external CPUs and the memory buffers. Two interface circuits are coupled between the external CPUs and the memory buffers to provide two data paths for transferring data between the external CPUs and the memory buffers. The data path control circuit contains two independent sequencing circuits for selecting memory buffers. This allows one data path to be used for reading or writing to a number of the memory buffers while the other data path is simultaneously used for a different operation for the rest of the memory buffers.