Patents Assigned to Multek Technologies Limited
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Patent number: 10772220Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are covered by a coverlay material and the covered inner core circuitry is exposed from the remaining layers of the PCB. The PCB having covered inner core circuitry is formed using a dummy core plus coverlay process. The select inner core circuitry is part of an inner core. The inner core corresponding to the covered inner core circuitry forms a flexible PCB portion. The flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the flexible PCB portion and the remaining rigid PCB portion.Type: GrantFiled: August 27, 2019Date of Patent: September 8, 2020Assignee: Multek Technologies LimitedInventors: J L Zhou, Pui Yin Yu
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Patent number: 10712398Abstract: A measuring system and method is configured to analyze numerous different types of interconnects having varying degrees of complexity. The measuring system and method characterizes an interconnect to be tested by a predefined reflection coefficient signature. Each specific interconnect is predefined by a reflection coefficient signature that is unique to that specific interconnect. Once the reflection coefficient signature is defined, a corresponding reflection envelope is defined which defines boundary limits about the reflection coefficient signature. Subsequent testing of the specific interconnect results in a measured reflection coefficient curve, which is compared to the corresponding reflection envelope. The specific interconnect under test is considered acceptable if the values of the measured reflection coefficient curve do not fall outside the reflection envelope.Type: GrantFiled: June 21, 2017Date of Patent: July 14, 2020Assignee: Multek Technologies LimitedInventor: Franz Gisin
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Publication number: 20200015365Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are covered by a coverlay material and the covered inner core circuitry is exposed from the remaining layers of the PCB. The PCB having covered inner core circuitry is formed using a dummy core plus coverlay process. The select inner core circuitry is part of an inner core. The inner core corresponding to the covered inner core circuitry forms a flexible PCB portion. The flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the flexible PCB portion and the remaining rigid PCB portion.Type: ApplicationFiled: August 27, 2019Publication date: January 9, 2020Applicant: Multek Technologies LimitedInventors: JL Zhou, Pui Yin Yu
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Patent number: 10458778Abstract: A measurement system measures various PCB panel characteristics, such as PCB panel thickness, surface feature thickness (height), surface feature width and length, and warpage. Various techniques are also described for steadying the PCB panel for measurement, whether the PCB panel is positioned horizontally or vertically. Z-height measurements as well as light intensity measurements can be used to determine the various PCB panel characteristics. Either the determined light intensity values, the determined Z-height values, or both can be used to determine pixel transition from one region, or material type, to another. Techniques are also provided to reduce PCB panel vibration and/or automatically adjusting a Z-height of the sensor to ensure a sampling point on the PCB panel is within an allowable Z-height range.Type: GrantFiled: November 17, 2017Date of Patent: October 29, 2019Assignee: Multek Technologies LimitedInventors: Michael James Glickman, Brendan Nagle
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Patent number: 10321560Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.Type: GrantFiled: January 13, 2016Date of Patent: June 11, 2019Assignee: Multek Technologies LimitedInventors: Pui Yin Yu, Mark Zhang, Jiawen Chen
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Patent number: 10292279Abstract: A disconnect cavity is formed within a PCB, where the disconnect cavity is electrically disconnected from a PCB landing layer. The disconnect cavity is formed using a plating resist process which does not require low flow prepreg nor selective copper etching. Plating resist is printed on a core structure selectively positioned within a PCB stack-up. The volume occupied by the plating resist forms a subsequently formed disconnect cavity. After lamination of the PCB stack-up, depth control milling, drilling and electroless copper plating are performed, followed by a plating resist stripping process to substantially remove the plating resist and all electroless copper plated to the plating resist, thereby forming the disconnect cavity. In a subsequent copper plating process, without electric connectivity copper cannot be plated to the side walls and bottom surface of the disconnect cavity, resulting in the disconnect cavity wall being electrically disconnected from the PCB landing layer.Type: GrantFiled: May 19, 2016Date of Patent: May 14, 2019Assignee: Multek Technologies LimitedInventors: Jiawen Chen, Pui Yin Yu
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Patent number: 10123603Abstract: The luggage lighting system includes a piece of luggage and a lighting module coupled to the luggage. In some embodiments, the lighting module is a fiber-optic lighting module. The luggage includes an outer surface, and the lighting module includes a light diffuser coupled to the outer surface. In some embodiments, the light diffuser is a fiber-optic light diffuser. The lighting module also includes a light source, such as a laser or a light emitting diode (LED). When the light source is powered on, the output light is directed through the light diffuser. The light diffuser is configured to output single or multiple colors of light, easily observed by someone looking at the luggage. The luggage lighting system is particularly useful for identifying one's luggage from surrounding pieces of luggage lacking the luggage lighting system.Type: GrantFiled: March 24, 2016Date of Patent: November 13, 2018Assignee: Multek Technologies LimitedInventors: Michael James Glickman, Mark Bergman, Joan Vrtis
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Patent number: 10064292Abstract: A PCB has multiple stacked layers laminated together, the laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure having a low adhesion to an underlying conductive layer, such as an LPI mixture. The LPI mixture defines cavity dimensions and enables the use of regular flow prepreg in the laminated stack.Type: GrantFiled: April 8, 2016Date of Patent: August 28, 2018Assignee: Multek Technologies LimitedInventor: Kwan Pen
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Patent number: 10009992Abstract: A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.Type: GrantFiled: December 2, 2016Date of Patent: June 26, 2018Assignee: Multek Technologies LimitedInventors: Joan K. Vrtis, Michael James Glickman, Todd Robinson, Hollese Galyon
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Patent number: 9999134Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.Type: GrantFiled: March 25, 2016Date of Patent: June 12, 2018Assignee: Multek Technologies LimitedInventors: Mark Zhang, Kwan Pen, Pui Yin Yu
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Patent number: 9992880Abstract: A printed circuit board (PCB) has multiple layers, where select portions of one or more conductive layers, referred to as core circuitry, form a semi-flexible PCB portion that is protected by an exposed prepreg layer. The semi-flexible PCB portion having an exposed prepreg layer is formed using a dummy core process that leaves the exposed prepreg layer smooth and undamaged. The core circuitry is part of a core structure. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The core structure is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.Type: GrantFiled: January 13, 2016Date of Patent: June 5, 2018Assignee: Multek Technologies LimitedInventors: Pui Yin Yu, Mark Zhang, Jiawen Chen
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Patent number: 9867290Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.Type: GrantFiled: August 24, 2015Date of Patent: January 9, 2018Assignee: Multek Technologies LimitedInventors: Kwan Pen, Pui Yin Yu
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Publication number: 20170339788Abstract: A printed circuit board has multiple stacked layers laminated together. A through hole is formed through the laminated stack, and plating is applied to the side walls of the though hole, thereby forming a plated through hole. Second through holes are then formed through the laminated stack, where each second through hole overlaps an edge of the plated through hole. By aligning the second through holes at the edge of the plated through hole, the plating of the plated through hole coincident with each second through hole is removed, thereby separating the plated through hole into two separate circuit paths. Forming second through holes in this manner effectively splits the circuit path of the plated through hole into multiple separate circuit paths, which increases the circuit density of the printed circuit board.Type: ApplicationFiled: June 7, 2016Publication date: November 23, 2017Applicant: Multek Technologies LimitedInventors: Znewa Zeng, Pui Yin Yu
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Publication number: 20170318685Abstract: A disconnect cavity is formed within a PCB, where the disconnect cavity is electrically disconnected from a PCB landing layer. The disconnect cavity is formed using a plating resist process which does not require low flow prepreg nor selective copper etching. Plating resist is printed on a core structure selectively positioned within a PCB stack-up. The volume occupied by the plating resist forms a subsequently formed disconnect cavity. After lamination of the PCB stack-up, depth control milling, drilling and electroless copper plating are performed, followed by a plating resist stripping process to substantially remove the plating resist and all electroless copper plated to the plating resist, thereby forming the disconnect cavity. In a subsequent copper plating process, without electric connectivity copper cannot be plated to the side walls and bottom surface of the disconnect cavity, resulting in the disconnect cavity wall being electrically disconnected from the PCB landing layer.Type: ApplicationFiled: May 19, 2016Publication date: November 2, 2017Applicant: Multek Technologies LimitedInventors: Jiawen Chen, Pui Yin Yu
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Publication number: 20170273195Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure having a low adhesion to an underlying conductive layer, such as an LPI mixture. The LPI mixture defines cavity dimensions and enables the use of regular flow prepreg in the laminated stack.Type: ApplicationFiled: April 8, 2016Publication date: September 21, 2017Applicant: Multek Technologies LimitedInventor: Kwan Pen
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Publication number: 20170271734Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes an embedded cavity, the perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask dam. The solder mask dam defines cavity dimensions and prevents prepreg resin flow into the cavity during lamination.Type: ApplicationFiled: March 31, 2016Publication date: September 21, 2017Applicant: Multek Technologies LimitedInventors: Pui Yin Yu, Jiawen Chen
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Publication number: 20170265298Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.Type: ApplicationFiled: March 25, 2016Publication date: September 14, 2017Applicant: Multek Technologies LimitedInventors: Mark Zhang, Kwan Pen, Pui Yin Yu
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Patent number: 9763327Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.Type: GrantFiled: August 24, 2015Date of Patent: September 12, 2017Assignee: Multek Technologies LimitedInventors: Kwan Pen, Pui Yin Yu
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Publication number: 20170238416Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are covered by a coverlay material and the covered inner core circuitry is exposed from the remaining layers of the PCB. The PCB having covered inner core circuitry is formed using a dummy core plus coverlay process. The select inner core circuitry is part of an inner core. The inner core corresponding to the covered inner core circuitry forms a flexible PCB portion. The flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the flexible PCB portion and the remaining rigid PCB portion.Type: ApplicationFiled: March 8, 2016Publication date: August 17, 2017Applicant: Multek Technologies LimitedInventors: JL Zhou, Pui Yin Yu
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Publication number: 20170164458Abstract: A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.Type: ApplicationFiled: December 2, 2016Publication date: June 8, 2017Applicant: Multek Technologies LimitedInventors: Joan K. Vrtis, Michael James Glickman, Todd Robinson, Hollese Galyon