Abstract: A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Abstract: Auto-tracking bit line reference schemes generate a “½ cell current” reference by programming reference cells to threshold voltages that are between threshold voltage levels used to represent data. A common word line can control both a selected memory cell and a reference cell to provide a reference current, and differential sense amplifiers can compare a bit line current to reference currents to thereby distinguish data values. Current through other reference cells can be mirrored to pull-up devices to further improve the tracking of the reference line and bit line currents. Embodiments of the invention can be used with binary and multiple-bit-per-cell memories and with a variety of memory array architectures and memory cell structures.

Abstract: Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of target threshold voltages. A first type of write operations reaches different target threshold voltages during different time intervals, but uses word line signals that optimize threshold voltage resolution regardless of the target threshold voltage. A second type uses bit line and/or source line biases that depend on the multi-bit data values being written so that different memory cells reach different target threshold voltage at about the same time. Source line biasing can also reduce bit line leakage current through unselected memory cells during read or verify operations. A memory includes divided source lines that permit separate data-dependent source biasing.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage.

Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased; after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.

Abstract: A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one array plane while the write path writes in another array plane and one or more blocks are being erased. The uniform block size permits a symmetric layout and provides maximum flexibility in storage of data, code, and parameters. The uniform block size also allows spare blocks in the array planes to replace of any defective blocks. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution to replace addresses corresponding to defective memory elements. To reduce access delays, part of the input address such as the row address goes directly to decoders, while another part of the input address such as the block address goes to the CAM array.

Abstract: A contactless Flash memory has memory cells between each pair of adjacent diffused lines and about half as many metal lines as diffused lines. Bank select cells at the top of a bank in the memory connect the metal lines to pairs of diffused lines that are offset relative to pairs of diffused lines connected to the metal lines via bank select cells at the bottom of the bank. Decoding circuits activate the bank select cells at one end of a bank to access memory cells in odd-numbered columns of the bank and activate the bank select cells at the other end to access memory cells in even-numbered columns of the bank. For the access, all metal lines to one side of a selected memory cell are grounded, while all metal lines on the other side are biased for reading or programming of the selected memory cell.

Abstract: A manufacturing method for a multiple-bit-per-cell memory tests memory arrays in the memory and separately sets the number of bits stored per cell in each memory array. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. The setting of the numbers of bits per cell for the respective memory arrays can maximize the memory capacity when some arrays perform better than expected. When the memory arrays perform worse than expected, the setting of the numbers of bits per cell can salvage the memory device even if the memory cannot provide the expected memory capacity.

Abstract: A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Abstract: A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. The Flash memory includes separate internal read and write paths connected to multiple array planes to permit a read in one array plane during a write in another array plane, further a third array plane can erase a block during the read and write operations. The uniform size, which permits a symmetric layout, is selected for efficient storage of parameters to provide maximum flexibility in allocation of storage. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks.

Abstract: A multi-bit-per-cell non-volatile memory performs refresh operations that move data to different physical storage locations. The movement of data may extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A contactless Flash memory uses a bank architecture with bank select devices and/or source line contacts at both ends of each bank. During programming, bank select devices at both ends of the bank supply currents to the memory cell being programmed, and/or diffused source lines conduct currents in both directions away from the memory cell being programmed. The multiple current paths reduce the current in any portion of the diffused lines and thereby reduce voltage drops in the diffused lines during programming. Accordingly, banks can have longer diffused lines (e.g., with twice as many cells per column of a bank) and still employ small bank select devices. The longer bank columns and smaller bank select devices result in an overall decrease in integrated circuit area for bank select devices, even though each bank has two bank select devices per diffused bit line.

Abstract: A multi-bit-per-cell non-volatile memory stores different portions of a data stream using different numbers of bits per cell. In particular, data that requires a high degree of data integrity (e.g., the header of a data frame) is stored using a relatively small number of bits per memory cell. Data that is more error-tolerant (e.g., the main data representing music, images, or video) is stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. Read circuitry decodes an output data stream and determines a number of bits read from each memory cell to generate the data stream. One such memory includes a decoder in the write circuitry and a decoder in the read circuitry, and another embodiment includes a single decoder that the write and read circuits share.

Abstract: A multi-bit-per-cell non-volatile memory periodically reads and rewrites data and thereby refreshes threshold voltages and removes the effects of threshold voltage drift. Accordingly, threshold voltages are kept in narrower ranges, and the narrow ranges allow more distinct levels for data values and allows storage of more bits per cell. A refresh interval is according to the size of windows for different multi-bit values and the measured or expected rate of threshold voltage drift. An on-chip refresh timer and arbitration logic selects when to initiate a refresh operation. A refresh can use a data buffer for temporary storage or can directly write data from one memory location to another. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In particular embodiments, shifts sectors-sized data blocks cyclically among sectors in an array, a bank, or an entire memory or alternatively shifts the data blocks between two configurations.

Abstract: A multiple-bit-per-cell memory includes multiple memory arrays, where the number of bits stored per cell is separately set for each of the memory arrays. Memory arrays that testing proves are accurate when writing, storing, and reading a larger number of bits per cell are set to store more bits per cell, and memory arrays that cannot accurately write, store, or read as many bits per cell are set to store fewer bits per cell. Accordingly, the setting of the numbers of bits per cell for the respective memory arrays can maximize the capacity of a memory when some arrays perform better than expected. When the memory arrays on average perform worse than expected, the setting of the numbers of bits per cell salvage the memory device even if the memory is unable to provide the total expected memory capacity. One implementation of the memory includes a register for the settings of the memory arrays and one or more analog/multi-level write and read circuits.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.

Abstract: A multi-level non-volatile memory includes one or more arrays of memory cells including storage cells and dummy cells. The memory observes or measures write operations that write dummy values to the dummy cells and from the observations or measurements selects parameters such as programming voltages or the duration of program cycles. The selection of parameters optimizes write precision within the available access time of a high bandwidth memory. Accessing dummy cells also allows the memory to reach a steady state before writing or reading of data begins. In particular, multiple pipelines sequentially start write operations, and writing of data begins when an equilibrium number of pipelines are performing write operations. Similarly, multiple read operation start before the reading of data for actual use. The stabilization is particularly critical when the pipelines share a power source.