Abstract: An oscillator is described. The oscillator includes segments of two-conductor transmission line being connected together by an odd number of connection means to form a closed loop. A plurality of current switches is connected to the conductors of the segments and a high impedance element, such as an inductor or transmission line, is connected to a conductor of at least one segment. The high impedance element sources current into the closed loop and the current switches sink current from one or the other of the conductors of the loop depending on the state of the switch. The switches cause a wave to be established and maintained on the loop and the wave changes the state of the switches as it oscillates. One embodiment of the switches employs npn transistors whose emitters are connected to a current source and another uses NMOS transistors.

Abstract: A multiphase mixer using a rotary traveling wave oscillator is disclosed. In addition to the oscillator, the mixer includes first and second mixer circuits. The rotary traveling wave oscillator generates a first set of N/2 phase and a second set of N/2 phases, where each phase has a frequency that is a factor of N/2 less than the incoming radio frequency signal. The first set of phases are sine signals and the second set of phases are cosine signals. The first mixer circuit generates a first down-converted signal from the first set of phases and the incoming rf signal. The second mixer circuit generates a second down-converted signal from the second set of phases and the rf signal.

Abstract: System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

Abstract: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

Abstract: System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

Abstract: A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results.

Abstract: A system and method of transmitting and receiving bit serial information is disclosed. In a differential embodiment, serial bits are transmitted by a pair of line-matched differential drivers that are ac coupled to a two-conductor transmission line. A receiver is ac coupled to the line and receives the transmitted serial information via a high pass filter. The receiver includes a level-triggered latch that provides a threshold for receiving the serial information, changes state to reflect the received information, and then clamps the received information to the state of the latch. In a single-ended embodiment, the ac-coupled receiver receives the bit serial information via a high pass filter. The resistance for the filter is an active device that also provides a voltage threshold for the receiver. The received bit serial information changes the state of a device which then alters the threshold, via hysteresis, for the net bit of serial information.

Abstract: A sampling circuit and method are disclosed. The sampling circuit includes a buffer, a holding capacitor, a set of switches, and at least two voltage references. The buffer drives buffered analog input signal via a first switch to a first node of holding capacitor. A second switch connects a second node of the holding capacitor to a first reference voltage. A third switch connects the second node of the holding capacitor to a second reference voltage. When the first and second switches are closed, charge accumulates on the holding capacitor. Opening the second switch terminates charging. The third switch biases the charged capacitor to the second reference voltage and the sampled output is taken from the first node of the holding capacitor. A rotary clock and control circuit provide the precise timing for the switches, especially the opening of the second switch, which determines the end of the sampling time.

Abstract: A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

Abstract: System and method for adjusting supply voltage to VCO to minimize affects of circuit noise on VCO. Method includes obtaining a number of data points each by incrementing a counter by the number of VCO periods during a phase of a local oscillator, changing the supply voltage, decrementing the counter by the number of VCO periods during another phase of the local oscillator, and then storing the net count. Then among the saved data points a data point is selected that is the point at or near where the VCO is least sensitive to supply changes and the VCO is set to operate at the supply voltage corresponding to this data point. A system includes a controller, up/down counter, local oscillator, and VCO. The counter counts the oscillations of the VCO and a stored net counts provide information as to where the VCO is least sensitive to the supply voltage.

Abstract: An oscillator is described. The oscillator includes segments of two-conductor transmission line being connected together by an odd number of connection means to form a closed loop. A plurality of current switches is connected to the conductors of the segments and a high impedance element, such as an inductor or transmission line, is connected to a conductor of at least one segment. The high impedance element sources current into the closed loop and the current switches sink current from one or the other of the conductors of the loop depending on the state of the switch. The switches cause a wave to be established and maintained on the loop and the wave changes the state of the switches as it oscillates. One embodiment of the switches employs npn transistors whose emitters are connected to a current source and another uses NMOS transistors.

Abstract: A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has a plurality of phases that are used in the time-to-digital converter to measure the time of a pulse created by the integrator. The edges of the pulse may optionally be sharpened by passing the pulse through a non-linear transmission line to improve the accuracy of the measurement process. To cut down on noise a tuned power network provides power to the switching devices of the rotary oscillator. Calibration is performed by fragmenting the sample and hold circuit and integrator and performing a closed loop calibration cycle on one of the fragments while the other fragments are joined together for the normal operation of the sample and hold and integrator circuits.

Abstract: A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprise steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said region are then divided into segments suitable for approximating lumped transmission-line LKR and relevant parameters determined so that time delays over each such segment are substantially equal to cycle time of desired frequency divided by twice the number of segments.

Abstract: A system and method for converting an analog signal to a digital signal is disclosed. The system includes a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit, an integrator and a time-to-digital converter. The multiphase oscillator has a plurality of phases that are used in the time-to-digital converter to measure the time of a pulse created by the integrator. The edges of the pulse may optionally be sharpened by passing the pulse through a non-linear transmission line to improve the accuracy of the measurement process. To cut down on noise a tuned power network provides power to the switching devices of the rotary oscillator. Calibration is performed by fragmenting the sample and hold circuit and integrator and performing a closed loop calibration cycle on one of the fragments while the other fragments are joined together for the normal operation of the sample and hold and integrator circuits.